參數(shù)資料
型號: IDT88P8342BHGI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 8/98頁
文件大?。?/td> 0K
描述: IC SPI3-SPI4 EXCHANGE 820-PBGA
標準包裝: 24
系列: *
其它名稱: 88P8342BHGI
16
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
Figure 6. PHY mode SPI-3 egress interface
Figure 5. Link mode SPI-3 egress interface
SPI-3 egress Link mode
The SPI Exchange receives status information from the PHY. The PHY
indicatesitsabilitytoreceivedata.Statusinformationforalllogicalportsisdirected
towards the packet fragment processor.
Status information is received from the PHY.
In packet mode, the SPI Exchange polls the PHY for the logical ports
associatedtoLIDsrangingfrom0uptoPOLL_LENGTHtofindlogicalportsthat
can accept data. The POLL_LENGTH field is defined in the SPI-3 egress
configurationregister.
In byte mode the SPI Exchange allows for direct status detection.
Thisstatusinformationisdirectlyforwardedtothepacketfragmentproces-
sor if enabled by the BURST_EN flag. When the BURST_EN flag is cleared
the only one packet fragment per LP is allowed into the SPI-3 egress buffers.
SPI-3 egress PHY mode
InPHYmode,theSPIExchangesendsdatatotheattachedLink-modedevice
aslongastheE_ENBsignalisasserted.TheSPI-3packetfragmentprocessor
transfers data to the SPI-3 egress buffers.
byte mode
packet mode
6370 drw38
IDT88P8342
(LINK MODE)
PHY
E_FCLK
E_MOD[1:0]
E_SOP
E_ENB
E_PRTY
E_Data[31:0]
E_ERR
ADDR[7:0]
PTPA
DTPA[3:0]
STPA
E_EOP
E_RSX
6370 drw39
IDT88P8342
(PHY MODE)
LINK
E_FCLK
E_MOD[1:0]
E_SOP
E_ENB
E_EOP
E_RSX
E_PRTY
E_Data[31:0]
E_ERR
RVAL
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相關代理商/技術參數(shù)
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IDT88P8342BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA(27x27) 包裝:散裝
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