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參數(shù)資料
| 型號(hào)： | IDT82V2082BFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 9/88頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 2CH 81BGA |
| 標(biāo)準(zhǔn)包裝： | 360 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 81-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 81-CABGA（8x8） |
| 包裝： | 托盤 |
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IDT82V2082
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PIN DESCRIPTION
17
May 4, 2009
TERM1
TERM2
I13
12
E3
E1
TERMn: Selects internal or external impedance matching for channel 1 and channel 2 in hardware control mode
0 = ternary interface with internal impedance matching network
1 = ternary interface with external impedance matching network in E1 mode; ternary interface with external impedance
matching network for receiver and ternary interface with internal impedance matching network for transmitter in T1/J1
mode.
(This applies to ZB die revision only.)
In software control mode, this pin should be connected to ground.
JA1
I
16
F2
JA[1:0]: Jitter attenuation position, bandwidth and the depth of FIFO select for channel 1 and channel 2 (only
used in hardware control mode)
00 = JA is disabled
01= JA in receiver, broad bandwidth, FIFO=64 bits
10 = JA in receiver, narrow bandwidth, FIFO=128 bits
11= JA in transmitter, narrow bandwidth, FIFO=128 bits
In software control mode, this pin should be connected to ground.
JA0
I
17
F3
See above.
MONT2
I
18
G2
MONT2: Receive Monitor gain select for channel 2
In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:
0= 0dB
1= 26dB
In software control mode, this pin should be connected to ground.
MONT1
I
19
G1
MONT1: Receive Monitor gain select for channel 1
In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:
0= 0dB
1= 26dB
In software control mode, this pin should be connected to ground.
RST
I21
J2
RST: Hardware Reset
The chip is forced to reset state if a low signal is input on this pin for more than 100ns. MCLK must be active during reset.
THZ
I
20
H1
THZ: Transmitter Driver High Impedance Enable
This signal enables or disables all transmitter drivers on a global basis. A low level on this pin enables the driver while
a high level on this pin places all drivers in high impedance state. Note that the functionality of the internal circuits is not
affected by this signal.
JTAG Signals
TRST
I
Pullup
1A1
TRST: JTAG Test Port Reset
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor. To ensure deter-
ministic operation of the test logic, TMS should be held high while the signal applied to TRST changes from low to high.
For normal signal processing, this pin should be connected to ground.
If JTAG is not used, this pin must be connected to ground.
TMS
I
Pullup
2
B1
TMS: JTAG Test Mode Select
This pin is used to control the test logic state machine and is sampled on the rising edge of TCK. TMS has an internal
pull-up resistor.
If JTAG is not used, this pin may be left unconnected.
TCK
I
3
B2
TCK: JTAG Test Clock
This is the input clock for JTAG. The data on TDI and TMS are clocked into the device on the rising edge of TCK while
the data on TDO is clocked out of the device on the falling edge of TCK. When TCK is idle at low state, all the stored-
state devices contained in the test logic will retain their state indefinitely.
If JTAG is not used, this pin may be left unconnected.
TDO
O
4
C2
TDO: JTAG Test Data Output
This output pin is high impedance normally and is used for reading all the serial configuration and test data from the test
logic. The data on TDO is clocked out of the device on the falling edge of TCK.
If JTAG is not used, this pin should be left unconnected.
Table-1 Pin Description (Continued)
Name
Type
TQFP80
Pin No.
FPBGA81
Pin No.
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V2082BFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 2CH 81BGA |
| IDT82V2082BFGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2082PF | 功能描述:IC LIU T1/J1/E1 2CH 80-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2082PF8 | 功能描述:IC LIU T1/J1/E1 2CH 80-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2082PFBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT |
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