參數(shù)資料
型號(hào)： IDT82V2082BFG
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 21/88頁(yè)
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 2CH 81BGA
標(biāo)準(zhǔn)包裝： 360
類型： 線路接口裝置（LIU）
規(guī)程： T1，E1，J1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 81-LFBGA
供應(yīng)商設(shè)備封裝： 81-CABGA（8x8）
包裝： 托盤
IDT82V2082
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
28
May 4, 2009
3.4.3
ADAPTIVE EQUALIZER
The adaptive equalizer can remove most of the signal distortion due to
intersymbol interference caused by cable attenuation. It can be enabled or
disabled by setting EQ_ON bit to ‘1’ or ‘0’ (RCF1, 0AH...).
When the adaptive equalizer is out of range, EQ_S bit (STAT0, 16H...)
will be set to ‘1’ to indicate the status of equalizer. If EQ_IES bit (INTES,
15H...) is set to ‘1’, any changes of EQ_S bit will generate an interrupt and
EQ_IS bit (INTS0, 18H...) will be set to ‘1’ if it is not masked. If EQ_IES bit
is set to ‘0’, only the ‘0’ to ‘1’ transition of the EQ_S bit will generate an inter-
rupt and EQ_IS bit will be set to ‘1’ if it is not masked. The EQ_IS bit will be
reset after being read.
The Amplitude/wave shape detector keeps on measuring the ampli-
tude/waveshapeoftheincomingsignalsduringanobservationperiod.This
observation period can be 32, 64, 128 or 256 symbol periods, as selected
by UPDW[1:0] bits (RCF2, 0BH...). A shorter observation period allows
quicker responses to pulse amplitude variation while a longer observation
period can minimize the possible overshoots. The default observation
period is 128 symbol periods.
Based on the observed peak value for a period, the equalizer will be
adjusted to achieve a normalized signal. LATT[4:0] bits (STAT1, 17H...)
indicate the signal attenuation introduced by the cable in approximately 2
dB per step.
3.4.4
RECEIVE SENSITIVITY
For short haul application, the Receive Sensitivity for both E1 and T1/
J1 is -10 dB. For long haul application, the receive sensitivity is -43 dB for
E1 and -36 dB for T1/J1.
When the chip is configured by hardware, the short haul or long haul
operating mode can be selected by setting EQn on a per channel basis. For
short haul mode, the Receive Sensitivity for both E1 and T1/J1 is -10 dB.
For long haul mode, the receive sensitivity is -43 dB for E1 and -36 dB for
T1/J1. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.4.5
DATA SLICER
The Data Slicer is used to generate a standard amplitude mark or a
space according to the amplitude of the input signals. The threshold can
be 40%, 50%, 60% or 70%, as selected by the SLICE[1:0] bits (RCF2,
0BH...). The output ofthe Data Slicer is forwardedto theCDR(Clock &Data
Recovery) unit or to the RDPn/RDNn pins directly if the CDR is disabled.
3.4.6
CDR (Clock & Data Recovery)
The CDR is used to recover the clock and data from the received signal.
The recovered clock tracks the jitter in the data output from the Data Slicer
and keeps the phase relationship between data and clock during the
absence of the incoming pulse. The CDR can also be by-passed in the Dual
Rail mode. When CDR is by-passed, the data from the Data Slicer is output
to the RDPn/RDNn pins directly.
3.4.7
DECODER
In T1/J1 applications, the R_MD[1:0] bits (RCF0, 09H...) is used to
selecttheAMIdecoderorB8ZSdecoder.InE1applications,theR_MD[1:0]
bits (RCF0, 09H...) are used to select the AMI decoder or HDB3 decoder.
When the chip is configured by hardware, the operation mode of receive
and transmit path can be selected by setting RXTXM[1:0] pins on a global
basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.4.8
RECEIVE PATH SYSTEM INTERFACE
The receive path system interface consists of RCLKn pin, RDn/RDPn
pin and RDNn pin. In E1 mode, the RCLKn outputs a recovered 2.048 MHz
clock.InT1/J1mode,theRCLKnoutputsarecovered1.544MHzclock.The
received data is updated on the RDn/RDPn and RDNn pins on the active
edge of RCLKn. The active edge of RCLKn can be selected by the
RCLK_SEL bit (RCF0, 09H...). And the active level of the data on RDn/
RDPn and RDNn can be selected by the RD_INV bit (RCF0, 09H...).
In hardware control mode, only the active edge of RCLKn can be
selected.IfRCLKEissettohigh,thefallingedgewillbechosenastheactive
edge of RCLKn. If RCLKE is set to low, the rising edge will be chosen as
the active edge of RCLKn. The active level of the data on RDn/RDPn and
RDNn is the same as that in software control mode.
Thereceiveddatacanbeoutputtothesystemsideintwodifferentways:
Single Rail or Dual Rail, as selected by R_MD bit [1] (RCF0, 09H...). In Sin-
gle Rail mode, only RDn pin is used to output data and the RDNn/CVn pin
is used to report the received errors. In Dual Rail Mode, both RDPn pin and
RDNn pin are used for outputting data.
In the receive Dual Rail mode, the CDR unit can be by-passed by setting
R_MD[1:0] to ‘11’ (binary). In this situation, the output data from the Data
Slicer will be output to the RDPn/RDNn pins directly, and the RCLKn out-
puts the exclusive OR (XOR)of the RDPn andRDNn. Thisis calledreceiver
slicer mode. In this case, the transmit path is still operating in Dual Rail
mode.
3.4.9
RECEIVE PATH POWER DOWN
The receive path can be powered down individually by setting R_OFF
bit (RCF0, 09H...) to ‘1’. In this case, the RCLKn, RDn/RDPn, RDNn and
LOSn will be logic low.
In hardware control mode, receiverpower down can be selected by pull-
ing RPDn pin to high on a per channel basis. Refer to 5 HARDWARE CON-
for more details.
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