參數(shù)資料
型號: IDT82V2081PPG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 41/68頁
文件大?。?/td> 0K
描述: IC LIU T1/J1/E1 1CH 44-TQFP
標準包裝: 80
類型: 線路接口裝置(LIU)
規(guī)程: T1/E1/J1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 44-LQFP
供應(yīng)商設(shè)備封裝: 44-TQFP(10x10)
包裝: 托盤
其它名稱: 800-2347
82V2081PPG
IDT82V2081PPG-ND
46
INDUSTRIAL
TEMPERATURE RANGES
SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
4.2.6
LINE STATUS REGISTERS
Table-47 STAT0: Line Status Register 0 (real time status monitor)
(R, Address = 17H)
Symbol
Bit
Default
Description
EQ_S
7
0
Equalizer status indication
= 0: In range
= 1: Out of range
IBLBA_S
6
0
In-band Loopback activate code receive status indication
= 0: No Inband Loopback activate code is detected
= 1: Activate signal is detected and then received over a period of more than t ms, with a bit error rate less than 10-
2. The bit remains set as long as the bit error rate does not exceed 10-2.
Note1:
If automatic remote loopback switching is disabled (ARLP = 0), t = 40 ms.
If automatic remote loopback switching is enabled (ARLP = 1), t = 5.1 s. The rising edge of this bit activates the
remote loopback operation in local end.
Note2:
If IBLBA_IM=0:
A ‘0’ to ‘1’ transition on this bit causes an activate code detected interrupt if IBLBA _IES bit is ‘0’;
Any changes of this bit causes an activate code detected interrupt if IBLBA _IES bit is set to ‘1’.
IBLBD_S
5
0
In-band Loopback deactivate code receive status indication
= 0: No Inband Loopback deactivate signal is detected
= 1: The Inband Loopback deactivate signal is detected and then received over a period of more than t, with a bit
error rate less than 10-2. The bit remains set as long as the bit error rate does not exceed 10-2.
Note1:
If automatic remote loopback switching is disabled (ARLP = 0), t = 40 ms.
If automatic remote loopback switching is enabled (ARLP = 1), t = 5.1 s. The rising edge of this bit disables the
remote loopback operation.
Note2:
If IBLBD_IM=0:
A ‘0’ to ‘1’ transition on this bit causes a deactivate code detected interrupt if IBLBD _IES bit is ‘0’
Any changes of this bit causes a deactivate code detected interrupt if IBLBD _IES bit is set to ‘1’
PRBS_S
4
0
Synchronous status indication of PRBS/QRSS (real time)
= 0: 215-1 (E1) PRBS or 220-1 (T1/J1) QRSS is not detected
= 1: 215-1 (E1) PRBS or 220-1 (T1/J1) QRSS is detected
Note:
If PRBS_IM=0:
A ‘0’ to ‘1’ transition on this bit causes a synchronous status detected interrupt if PRBS _IES bit is ‘0’.
Any changes of this bit causes an interrupt if PRBS_IES bit is set to ‘1’.
TCLK_LOS
3
0
TCLK loss indication
= 0: Normal
= 1: TCLK pin has not toggled for more than 70 MCLK cycles.
Note:
If TCLK_IM=0:
A ‘0’ to ‘1’ transition on this bit causes an interrupt if TCLK _IES bit is ‘0’.
Any changes of this bit causes an interrupt if TCLK_IES bit is set to ‘1’.
DF_S
2
0
Line driver status indication
= 0: Normal operation
= 1: Line driver short circuit is detected.
Note:
If DF_IM=0
A ‘0’ to ‘1’ transition on this bit causes an interrupt if DF _IES bit is ‘0’.
Any changes of this bit causes an interrupt if DF_IES bit is set to ‘1’.
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