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參數(shù)資料
| 型號(hào)： | IDT82P2828BHG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 2/154頁(yè) |
| 文件大小： | 0K |
| 描述： | IC LIU T1/J1/E1 28+1CH 640-PBGA |
| 標(biāo)準(zhǔn)包裝： | 5 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 640-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 640-PBGA-EP（31x31） |
| 包裝： | 托盤 |
| 其它名稱： | 82P2828BHG |
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February 6, 2009
IDT82P2828
2009 Integrated Device Technology, Inc.
DSC-6248/3
28(+1) Channel
High-Density T1/E1/J1
Line Interface Unit
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
FEATURES
Integrates 28+1 channels T1/E1/J1 short haul line interface
units for 100
T1, 120 E1, 110 J1 twisted pair cable and
75
E1 coaxial cable applications
Per-channel configurable Line Interface options
Supports various line interface options
– Differential and Single Ended line interfaces
– true Single Ended termination on primary and secondary side of trans-
former for E1 75
coaxial cable applications
– transformer-less for Differential interfaces
Fully integrated and software selectable receive and transmit
termination
– Option 1: Fully Internal Impedance Matching with integrated receive
termination resistor
– Option 2: Partially Internal Impedance Matching with common external
resistor for improved device power dissipation
– Option 3: External impedance Matching termination
Supports global configuration and per-channel configuration to
T1, E1 or J1 mode
Per-channel programmable features
Provides T1/E1/J1 short haul waveform templates and user-
programmable arbitrary waveform templates
Provides two JAs (Jitter Attenuator) for each channel of receiver
and transmitter
Supports AMI/B8ZS (for T1/J1) and AMI/HDB3 (for E1) encoding
and decoding
Per-channel System Interface options
Supports Single Rail, Dual Rail with clock or without clock and
sliced system interface
Integrated Clock Recovery for the transmit interface to recover
transmit clock from system transmit data
Per-channel system and diagnostic functions
Provides transmit driver over-current detection and protection
with optional automatic high impedance of transmit interface
Detects and generates PRBS (Pseudo Random Bit Sequence),
ARB (Arbitrary Pattern) and IB (Inband Loopback) in either
receive or transmit direction
Provides defect and alarm detection in both receive and transmit
directions.
– Defects include BPV (Bipolar Violation) /CV (Code Violation) and EXZ
(Excessive Zeroes)
– Alarms include LLOS (Line LOS), SLOS (System LOS), TLOS
(Transmit LOS) and AIS (Alarm Indication Signal)
Programmable LLOS detection /clear levels. Compliant with ITU
and ANSI specifications
Various pattern, defect and alarm reporting options
– Serial hardware LLOS reporting (LLOS, LLOS0) for all 29 channels
– Configurable per-channel hardware reporting with RMF/TMF
(Receive /Transmit Multiplex Function)
– Register access to individual registers or 16-bit error counters
Supports Analog Loopback, Digital Loopback and Remote
Loopback
Supports T1.102 line monitor
Channel 0 monitoring options
Channel 0 can be configured as monitoring channel or regular
channel to increase capacity
Supports all internal G.772 Monitoring for Non-Intrusive
Monitoring of any of the 28 channels of receiver or transmitter
Jitter Measurement per ITU O.171
Hitless Protection Switching (HPS) without external Relays
Supports 1+1 and 1:1 hitless protection switching
Asynchronous hardware control (OE, RIM) for fast global high
impedance of receiver and transmitter (hot switching between
working and backup board)
High impedance transmitter and receiver while powered down
Per-channel register control for high impedance, independent for
receiver and transmitter
Clock Inputs and Outputs
Flexible master clock (N x 1.544 MHz or N x 2.048 MHz) (1
≤ N ≤
8, N is an integer number)
Two selectable reference clock outputs
– from the recovered clock of any of the 29 channels
– from external clock input
– from device master clock
Integrated clock synthesizer can multiply or divide the reference
clock to a wide range of frequencies: 8 KHz, 64 KHz, 2.048 MHz,
4.096 MHz, 8.192 MHz, 19.44 MHz and 32.768 MHz
Cascading is provided to select a single reference clock from
multiple devices without the need for any external logic
Microprocessor Interface
Supports Serial microprocessor interface and Parallel Intel /
Motorola Non-Multiplexed /Multiplexed microprocessor interface
Other Key Features
IEEE1149.1 JTAG boundary scan
Two general purpose I/O pins
3.3 V I/O with 5 V tolerant inputs
3.3 V and 1.8 V power supply
Package: 640-pin TEPBGA (31 mm X 31 mm)
Applicable Standards
AT&T Pub 62411 Accunet T1.5 Service
ANSI T1.102, T1.403 and T1.231
Bellcore TR-TSY-000009, GR-253-CORE and GR-499-CORE
ETSI CTR12/13
ETS 300166 and ETS 300 233
G.703, G.735, G.736, G.742, G.772, G.775, G.783 and G.823
O.161
ITU I.431 and ITU O.171
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相關(guān)代理商/技術(shù)參數(shù) |
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| IDT82P2916 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:16-Channel High-Density T1/E1/J1 Line Interface Unit |
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| IDT82P5088BBBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter |
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