- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1924 > IDT82P2521BHG (IDT, Integrated Device Technology Inc)IC LIU E1 21+1CH SHORT 640-PBGA PDF資料下載
參數(shù)資料
| 型號： | IDT82P2521BHG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 90/147頁 |
| 文件大小： | 0K |
| 描述： | IC LIU E1 21+1CH SHORT 640-PBGA |
| 標(biāo)準(zhǔn)包裝： | 5 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 640-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 640-PBGA-EP（31x31） |
| 包裝： | 托盤 |
| 其它名稱： | 82P2521BHG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁當(dāng)前第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁
IDT82P2521
21(+1) CHANNEL HIGH-DENSITY E1 LINE INTERFACE UNIT
Functional Description
47
December 7, 2005
3.4.5
PRBS, QRSS, ARB AND IB PATTERN GENERATION AND
DETECTION
The pattern includes: Pseudo Random Bit Sequence (PRBS), Quasi-
Random Signal Source (QRSS), Arbitrary Pattern (ARB) and Inband
Loopback (IB).
3.4.5.1 Pattern Generation
The pattern can be generated in the receive path or the transmit
path, as selected by the PG_POS bit (b3, PG,...).
The pattern to be generated is selected by the PG_EN[1:0] bits
(b5~4, PG,...).
If PRBS is selected, three kinds of PRBS patterns with maximum
zero restriction according to ITU-T O.151 and AT&T TR62411 are
provided. They are: (2^20 - 1) QRSS per O.150-4.5, (2^15 - 1) PRBS
per O.152 and (2^11 - 1) PRBS per O.150, as selected by the
PRBG_SEL[1:0] bits (b1~0, PG,...).
If ARB is selected, the content is programmed in the ARB[23:0] bits
(b7~0, ARBH~ARBM~ARBL,...).
If IB is selected, the IB generation is in compliance with ANSI T1.403.
The length of the IB code can be 3 to 8 bits, as determined by the
IBGL[1:0] bits (b5~4, IBL,...). The content is programmed in the IBG[7:0]
bits (b7~0, IBG,...).
The selected pattern is transmitted repeatedly until the PG_EN[1:0]
bits (b5~4, PG,...) is set to ‘00’.
When pattern is generated in the receive path, the reference clock is
XCLK or the recovered clock from the received signal, as selected by
the PG_CK bit (b6, PG,...). The selected reference clock is also output
on RCLKn (if available).
When pattern is generated in the transmit path, the reference clock is
The transmit clock refers to the clock input on TCLKn (in Transmit Single
Rail NRZ Format mode and in Transmit Dual Rail NRZ Format mode) or
the clock recovered from the data input on TDPn and TDNn (in Transmit
Dual Rail RZ Format mode).
In summary, do the followings step by step to generate pattern:
Select the generation direction by the PG_POS bit (b3, PG,...);
Select the reference clock by the PG_CK bit (b6, PG,...);
Select the PRBS pattern by the PRBG_SEL[1:0] bits (b1~0, PG,...)
when PRBS is to be generated; program the ARB pattern in the
ARB[23:0] bits (b7~0, ARBH~ARBM~ARBL,...) when ARB is to be
generated; or set the length and the content of the IB code in the
respectively when IB is to be generated;
Set the PG_EN[1:0] bits (b5~4, PG,...) to generate the pattern.
If PRBS or ARB is selected to be generated, the following two steps
can be optionally implemented after the pattern is generated:
Insert a single bit error by writing ‘1’ to the ERR_INS bit (b5,
Invert the generated pattern by setting the PAG_INV bit (b2,
If pattern is generated in the receive path, the generated pattern
should be encoded by using AMI HDB3 in Receive Dual Rail NRZ
Format mode, Receive Dual Rail RZ Format mode and Receive Dual
Rail Sliced mode. The encoding rule is selected by the R_CODE bit (b2,
If pattern is generated in the transmit path, the generated pattern
should be encoded by using AMI HDB3. The encoding rule is selected
by the T_CODE bit (b2, TCF1,...).
The pattern generation is shown in Figure-24 and Figure-25.
Figure-24 Pattern Generation (1)
Figure-25 Pattern Generation (2)
The priority of pattern generation is higher than that of AIS genera-
tion. If they are generated in the same direction, the generated pattern
will overwrite the generated AIS.
1. XCLK is derived from MCLK. It is 2.048 MHz .
PRBS/ARB/IB
pattern generator
PG_POS
CHn
TDPn/TDNn/TCLKn
RDPn/RDNn/RCLKn
TTIPn/TRINGn
RTIPn/RRINGn
XCLK
PG_EN[1:0]
TCLK/RCLK
PG_CK
PRBS generation
2^11-1
2^15-1
2^20-1
invert
ERR_INS
PAG_INV
Single bit error
insert
24 bits ARB
ARB[23:0]
PG_EN[1:0]
PRBG_SEL[1:0]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT82P2816BBG | IC LINE INTERFACE UNIT 416-PBGA |
| IDT82P2821BH | IC LIU T1/J1/E1 21+1CH 640-PBGA |
| IDT82P2828BHG | IC LIU T1/J1/E1 28+1CH 640-PBGA |
| IDT82P2916BFG | IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P5088BBG | IC LIU T1/E1/J1 OCTAL 256PBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82P2521BHGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:21(1) Channel High-Density E1 Line Interface Unit |
| IDT82P2808 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:8(+1) Channel High-Density T1/E1/J1 Line Interface Unit |
| IDT82P2808BB | 功能描述:IC LIU T1/J1/E1 8+1CH 416-PBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| IDT82P2808BBG | 功能描述:IC LIU T1/J1/E1 8+1CH 416-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| IDT82P2816 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:16(+1) Channel High-Density T1/E1/J1 Line Interface Unit |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。