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參數(shù)資料
| 型號： | IDT82P2521BHG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 86/147頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E1 21+1CH SHORT 640-PBGA |
| 標準包裝： | 5 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 640-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 640-PBGA-EP（31x31） |
| 包裝： | 托盤 |
| 其它名稱： | 82P2521BHG |
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IDT82P2521
21(+1) CHANNEL HIGH-DENSITY E1 LINE INTERFACE UNIT
Functional Description
43
December 7, 2005
3.4.3
LOSS OF SIGNAL (LOS) DETECTION
The IDT82P2521 detects three kinds of LOS:
LLOS: Line LOS, detected in the receive path;
SLOS: System LOS, detected in the transmit system side;
TLOS: Transmit LOS, detected in the transmit line side.
3.4.3.1 Line LOS (LLOS)
The amplitude and density of the data received from the line side are
monitored. When the amplitude of the data is less than Q Vpp for N
consecutive pulse intervals, LLOS is declared. When the amplitude of
the data is more than P Vpp and the average density of marks is at least
12.5% for M consecutive pulse intervals starting with a mark, LLOS is
cleared. Here Q is defined by the ALOS[2:0] bits (b6~4, LOS,...). P is the
sum of Q and 250 mVpp. N and M are defined by the LAC bit (b7,
LLOS detection supports G.775 and ETSI 300233/I.431. The criteria
are selected by the LAC bit (b7, LOS,...).
When LLOS is detected, the LLOS_S bit (b0, STAT0,...) will be set. A
transition from ‘0’ to ‘1’ on the LLOS_S bit (b0, STAT0,...) or any transi-
tion (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the LLOS_S bit (b0, STAT0,...) will
set the LLOS_IS bit (b0, INTS0,...) to ‘1’, as selected by the LOS_IES bit
(b1, INTES,...). When the LLOS_IS bit (b0, INTS0,...) is ‘1’, an interrupt
will be reported by INT if not masked by the LLOS_IM bit (b0, INTM0,...).
Two pins (LLOS0 and LLOS) are dedicated to LLOS indication.
Whether LLOS is detected in channel 0 or not, LLOS0 is high for a
CLKE1 clock cycle to indicate the channel 0 position on LLOS. LLOS
indicates LLOS status of all 22 channels in a serial format and repeats
every 22 cycles. Refer to Figure-22. LLOS0 and LLOS are updated on
the rising edge of CLKE1. When the clock output on CLKE1 is disabled,
LLOS0 and LLOS will be held in High-Z state. The output on CLKE1 is
controlled by the CLKE1_EN bit (b3, CLKG) and the CLKE1 bit (b2,
CLKG). Refer to section 8.9 on page 129 for CLKE1 timing characteris-
tics.
LLOS may be counted by an internal Error Counter or may be indi-
cated by the RMFn pin. Refer to Section 3.4.6 Error Counter and
Section 3.4.7.1 RMFn Indication respectively.
During LLOS, in Receive Single Rail NRZ Format mode, Receive
Dual Rail NRZ Format mode and Receive Dual Rail RZ Format mode,
RDn and RDPn/RDNn output low level. In Receive Dual Rail Sliced
mode RDPn/RDNn still output sliced data. RCLKn (if available) outputs
During LLOS, if any of AIS, pattern generation in the receive path or
Digital Loopback is enabled, RDn, RDPn/RDNn and RCLKn output
corresponding data and clock, and the setting of the RCKH bit (b7,
RCF0,...) is ignored. Refer to the corresponding chapters for details.
Figure-22 LLOS Indication on Pins
1. XCLK is derived from MCLK. It is 2.048 MHz .
Table-9 LLOS Criteria
Operation
Mode
LAC
Criteria
LLOS Declaring
LLOS Clearing
E1
0
G.775
below Q Vpp, N = 32 bits
above P Vpp, 12.5% mark density with less than 16 consecutive zeros, M = 32 bits
1
ETSI 300233/
I.431
below Q Vpp, N = 2048 bits
above P Vpp, 12.5% mark density with less than 16 consecutive zeros, M = 32 bits
One LLOS Indication Cycle
LLOS
LLOS0
CLKE1
CH0 CH1 CH2
CH21 CH0
01
2
21
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82P2521BHGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:21(1) Channel High-Density E1 Line Interface Unit |
| IDT82P2808 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:8(+1) Channel High-Density T1/E1/J1 Line Interface Unit |
| IDT82P2808BB | 功能描述:IC LIU T1/J1/E1 8+1CH 416-PBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| IDT82P2808BBG | 功能描述:IC LIU T1/J1/E1 8+1CH 416-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| IDT82P2816 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:16(+1) Channel High-Density T1/E1/J1 Line Interface Unit |
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