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| 型號(hào)： | IDT82P2284BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 340/363頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | TXRX T1/J1/E1 4CHAN 208-PBGA |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 類(lèi)型： | 收發(fā)器 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 1.8V, 3.3V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 208-BGA |
| 供應(yīng)商設(shè)備封裝： | 208-PBGA（17x17） |
| 包裝： | 托盤(pán) |
| 其它名稱(chēng)： | 82P2284BB |
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IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
78
February 25, 2008
In the Receive Clock Slave mode, the data on the system interface is
clocked by the RSCKn. The active edge of the RSCKn used to sample
the pulse on the RSFSn is determined by the FE bit. The active edge of
the RSCKn used to update the data on the RSDn and RSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the RSFSn is ahead. The speed of the RSCKn can be selected by
the CMS bit to be the same rate as the data rate on the system side
(2.048 MHz) or double the data rate (4.096 MHz). If all four links use the
RSCK[1] and RSFS[1] to output the data, the CMS bit of the four links
should be set to the same value. If the speed of the RSCKn is double the
data rate, there will be two active edges in one bit duration. In this case,
the EDGE bit determines the active edge to update the data on the
RSDn and RSIGn pins. The pulse on the RSFSn pin is always sampled
on its first active edge.
In the Receive Clock Slave mode, the RSFSn asserts at a rate of
integer multiple of 125
s to indicate the start of a frame. The active
polarity of the RSFSn is selected by the FSINV bit. If the pulse on the
RSFSn pin is not an integer multiple of 125
s, this detection will be indi-
cated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will
be reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.2.3 Receive Multiplexed Mode
In the Receive Multiplexed mode, one multiplexed bus is used to
output the data from all four links. The data of Link 1 to Link 4 is byte-
interleaved output on the multiplexed bus 1. When the data from the four
links is output on one multiplexed bus, the sequence of the data is
arranged by setting the timeslot offset. The data from different links on
one multiplexed bus must be shifted at a different timeslot offset to avoid
data mixing.
In the Receive Multiplexed mode, the timing signal on the MRSCK
pin and the framing pulse on the MRSFS pin are provided by the system
side and common to all four links. The signaling bits on the MRSIGA
(MRSIGB) pin are per-timeslot aligned with the corresponding data on
the MRSDA (MRSDB) pin.
In the Receive Multiplexed mode, the data on the system interface is
clocked by the MRSCK. The active edge of the MRSCK used to sample
the pulse on the MRSFS is determined by the FE bit. The active edge of
the MRSCK used to update the data on the MRSDA (MRSDB) and
MRSIGA (MRSIGB) is determined by the DE bit. The FE bit and the DE
bit of the four links should be set to the same value respectively. If the
FE bit and the DE bit are not equal, the pulse on the MRSFS is ahead.
The MRSCK can be selected by the CMS bit to be the same rate as the
data rate on the system side (8.192 MHz) or double the data rate
(16.384 MHz). The CMS bit of the four links should be set to the same
value. If the speed of the MRSCK is double the data rate, there will be
two active edges in one bit duration. In this case, the EDGE bit deter-
mines the active edge to update the data on the MRSDA (MRSDB) and
MRSIGA (MRSIGB) pins. The pulse on the MRSFS pin is always
sampled on its first active edge.
In the Receive Multiplexed mode, the MRSFS asserts at a rate of
integer multiple of 125
s to indicate the start of a frame. The active
polarity of the MRSFS is selected by the FSINV bit. The FSINV bit of the
four links should be set to the same value. If the pulse on the MRSFS
pin is not an integer multiple of 125
s, this detection will be indicated by
the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will be
reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.2.4 Offset
Except that in the Receive Master mode, when the OHD bit, the
SMFS bit and the CMFS bit are set to TS1 and TS16 overhead indica-
tion, the bit offset and timeslot offset are both supported in all the other
conditions. The offset is between the framing pulse on RSFSn/MRSFS
pin and the start of the corresponding frame output on the RSDn/
MRSDA(MRSDB) pin. The signaling bits on the RSIGn/
MRSIGA(MRSIGB) pin are always per-timeslot aligned with the data on
the RSDn/MRSDA(MRSDB) pin.
Refer to Chapter 3.17.1.4 Offset for the base line without offset in
different operating modes and the configuration of the offset.
In Non-multiplexed mode, the timeslot offset can be configured from
0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the timeslot
offset can be configured from 0 to 127 timeslots (0 & 127 are included).
3.17.2.5 Output On RSDn/MRSDA(MRSDB) & RSIGn/
MRSIGA(MRSIGB)
The output on the RSDn/MRSDA(MRSDB) and the RSIGn/
MRSIGA(MRSIGB) pins can be configured by the TRI bit of the corre-
sponding link to be in high impedance state or to output the processed
data stream.
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| IDT82P2284BB8 | 功能描述:TXRX T1/J1/E1 4CHAN 208-PBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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| IDT82P2284BBG8 | 功能描述:TXRX T1/J1/E1 4CHAN 208-PBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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