參數(shù)資料
型號(hào)： IDT82P2281PF
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 338/371頁(yè)
文件大?。?/td> 0K
描述： TXRX T1/E1/J1 LONG/SHORT 80-TQFP
標(biāo)準(zhǔn)包裝： 30
類型： 收發(fā)器
規(guī)程： T1，E1，J1
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-TQFP（14x14）
包裝： 托盤
其它名稱： 82P2281PF
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IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
69
August 20, 2009
In Non-multiplexed mode, the channel offset can be configured
from 0 to 23 channels (0 & 23 are included). In Multiplexed mode, the
channel offset can be configured from 0 to 127 channels (0 & 127 are
included).
3.17.1.5
Output On RSD/MRSD & RSIG/MRSIG
The output on the RSD/MRSD and the RSIG/MRSIG pins can be
configured by the TRI bit to be in high impedance state or to output the
processed data stream.
3.17.2
E1 MODE
In E1 mode, the Receive System Interface can be set in Non-multi-
plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
RSD pin is used to output the received data at the bit rate of 2.048 Mb/s.
While in the Multiplexed Mode, the received data from the link is byte
interleaved to form one high speed data stream and output on the
MRSD pin at the bit rate of 8.192 Mb/s.
In the Non-multiplexed mode, if the RSCK is from outside, the
receive system interface is in Receive Clcok Slave mode, otherwise if
the device outputs clock to RSCK from itself, the receive system inter-
face is in Receive Clcok Master mode.
In the Receive Clock Master mode, if RSCK outputs pulses during
the entire E1 frame, the Receive System Interface is in Receive Clock
Master Full E1 mode. If only the clocks aligned to the selected timeslots
are output on RSCK, the Receive System Interface is in Receive Clock
Master Fractional E1 mode.
Table 40 summarizes how to set the receive system interface into
various operating modes and the pins’ direction of the receive system
interface in different operating modes.
3.17.2.1
Receive Clock Master Mode
In the Receive Clock Master mode, the timing signal on the RSCK
pin and framing pulse on the RSFS pin are used to output the data on
the RSD pin. The signaling bits on the RSIG pin are per-timeslot aligned
with the data on the RSD pin.
In the Receive Clock Master mode, the data on the system inter-
face is clocked by the RSCK. The active edge of the RSCK used to
update the pulse on the RSFS is determined by the FE bit. The active
edge of the RSCK used to update the data on the RSD and RSIG is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the RSFS is ahead.
In the Receive Clock Master mode, the RSFS can indicate the
Basic frame, CRC Multi-frame, Signaling Multi-frame, or both the CRC
Multi-frame and Signaling Multi-frame, or the TS1 and TS 16 overhead.
All the indications are selected by the OHD bit, the SMFS bit and the
CMFS bit. The active polarity of the RSFS is selected by the FSINV bit.
The Receive Clock Master mode includes two sub-modes: Receive
Clock Master Full E1 mode and Receive Clock Master Fractional E1
mode.
3.17.2.1.1
Receive Clock Master Full E1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCK is a
standard 2.048 MHz clock, and the data in all 32 timeslots in a standard
E1 frame is clocked out by the RSCK.
3.17.2.1.2
Receive Clock Master Fractional E1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCK is a
gapped 2.048 MHz clock (no clock signal during the selected timeslot).
The RSCK is gapped during the timeslots or the Bit 8 duration by
selecting the G56K & GAP bits in the Receive Payload Control. The data
in the corresponding gapped duration is a don't care condition.
3.17.2.2
Receive Clock Slave Mode
In the Receive Clock Slave mode, the timing signal on the RSCK
pin and framing pulse on the RSFS pin to output the data on the RSD
pin are provided by the system side. The signaling bits on the RSIG pin
are per-timeslot aligned with the data on the RSD pin.
In the Receive Clock Slave mode, the data on the system interface
is clocked by the RSCK. The active edge of the RSCK used to sample
Table 40: Operating Modes Selection In E1 Receive Path
RMUX RMODE G56K, GAP
Operating Mode
Receive System Interface Pin
Input
Output
0
00
Receive Clock Master Full E1
X
RSCK, RSFS, RSD, RSIG
not both 0s 1 Receive Clock Master Fractional E1
1
X
Receive Clock Slave
RSCK, RSFS
RSD, RSIG
1
X
Receive Multiplexed
MRSCK, MRSFS
MRSD, MRSIG
NOTE:
1. When the G56K, GAP bits in RPLC indirect registers are set, the PCCE bit must be set to ‘1’.
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IDT82P2281PF8 功能描述:TXRX T1/E1/J1 LONG/SHORT 80-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
IDT82P2281PFBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Single T1/E1/J1 Long Haul / Short Haul Transceiver
IDT82P2281PFG 功能描述:TXRX T1/E1/J1 LONG/SHORT 80-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:驅(qū)動(dòng)器 驅(qū)動(dòng)器/接收器數(shù):4/0 規(guī)程:RS422 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC N 包裝:帶卷 (TR)
IDT82P2281PFG8 功能描述:TXRX SGL T1/E1/J1 80-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
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