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參數(shù)資料
| 型號： | IDT82P2281PF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 333/371頁 |
| 文件大小： | 0K |
| 描述： | TXRX T1/E1/J1 LONG/SHORT 80-TQFP |
| 標準包裝： | 30 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應商設備封裝： | 80-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 82P2281PF |
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IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
64
August 20, 2009
3.17
RECEIVE SYSTEM INTERFACE
The Receive System Interface determines how to output the
received data stream to the system backplane. The timing clocks and
framing pulses can be provided by the system backplane or obtained
from the far end. The Receive System Interface supports various config-
urations to meet various requirements in different applications.
3.17.1
T1/J1 MODE
In T1/J1 mode, the Receive System Interface can be set in Non-
multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the RSD pin is used to output the received data at the bit rate of 1.544
Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the Multiplexed
Mode, the received data from the link is converted to 2.048 Mb/s format
and byte interleaved to form one high speed data stream and output on
the MRSD pin at the bit rate of 8.192 Mb/s.
In the Receive Clock Master mode, the device outputs clock
(M)RSCKn/(M)RSFSn. This clock is derived from line side signal or
MCLK (When LOSS).
In the Receive Clock Master mode, if RSCK outputs pulses during
the entire T1/J1 frame, the Receive System Interface is in Receive Clock
Master Full T1/J1 mode. If only the clocks aligned to the selected chan-
nels are output on RSCK, the Receive System Interface is in Receive
Clock Master Fractional T1/J1 mode.
In the Receive Clock Slave mode, outside inputs clock (M)RSCKn/
(M)RSFSn to the device. To avoid shatter data, this clock should keep
the same source with line side. If the backplane data rate is 2.048 Mb/s,
means T1 mode E1 rate, the receive data(1.544 Mb/s) should be
mapped to 2.048 Mb/s,there are 3 kinds of mapping schemes.
In the Receive Multiplexed mode, since the received data should
be converted to 2.048 Mb/s format first and then multiplexed to 8.192
Mb/s, there are still 3 kinds of schemes to be selected.
Table 39 summarizes how to set the Receive System Interface into
various operating modes and the pins’ direction of the Receive System
Interface in different operating modes.
3.17.1.1
Receive Clock Master Mode
In the Receive Clock Master mode, the timing signal on the RSCK
pin and framing pulse on the RSFS pin are used to output the data on
the RSD pin. The signaling bits on the RSIG pin are per-channel aligned
with the data on the RSD pin.
In the Receive Clock Master mode, the data on the system inter-
face is clocked by the RSCK. The active edge of the RSCK used to
update the pulse on the RSFS is determined by the FE bit. The active
edge of the RSCK used to update the data on the RSD and RSIG is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the RSFS is ahead.
In the Receive Clock Master mode, the RSFS can indicate each F-
bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. In SF
format, the RSFS can also indicate every second F-bit or the first F-bit of
every second SF multi-frame. All the indications are selected by the
CMFS bit and the ALTIFS bit. The active polarity of the RSFS is selected
by the FSINV bit.
The Receive Clock Master mode includes two sub-modes: Receive
Clock Master Full T1/J1 mode and Receive Clock Master Fractional T1/
J1 mode.
3.17.1.1.1
Receive Clock Master Full T1/J1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCK is a
standard 1.544 MHz clock, and the data in the F-bit and all 24 channels
in a standard T1/J1 frame are clocked out by the RSCK.
3.17.1.1.2
Receive Clock Master Fractional T1/J1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCK is a
gapped 1.544 MHz clock (no clock signal during the selected position).
The RSCK is gapped during the F-bit if the FBITGAP bit is set to ‘1’.
The RSCK is also gapped during the channels or the Bit 8 duration by
Table 39: Operating Modes Selection In T1/J1 Receive Path
RMUX RMODE
G56K, GAP /
FBITGAP
MAP[1:0] 2
Operating Mode
Receive System Interface Pin
Input
Output
0
00 / 0
X
Receive Clock Master Full T1/J1
X
RSCK, RSFS,
RSD, RSIG
not all 0s 1
Receive Clock Master Fractional T1/J1
1X
00
Receive Clock Slave - T1/J1 Rate
RSCK, RSFS
RSD, RSIG
01
Receive Clock Slave - T1/J1 Mode E1 Rate per G.802
10
Receive Clock Slave - T1/J1 Mode E1 Rate per One Filler Every Four CHs
11
Receive Clock Slave - T1/J1 Mode E1 Rate per Continuous CHs
1X
X
01
Receive Multiplexed - T1/J1 Mode E1 Rate per G.802
MRSCK, MRSFS
MRSD, MRSIG
10
Receive Multiplexed - T1/J1 Mode E1 Rate per One Filler Every Four CHs
11
Receive Multiplexed - T1/J1 Mode E1 Rate per Continuous CHs
NOTE:
1. When the G56K, GAP bits in RPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. The MAP[1:0] bits can not be set to ‘00’ in the Receive Multiplexed mode.
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| IDT82P2281PF8 | 功能描述:TXRX T1/E1/J1 LONG/SHORT 80-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82P2281PFBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Single T1/E1/J1 Long Haul / Short Haul Transceiver |
| IDT82P2281PFG | 功能描述:TXRX T1/E1/J1 LONG/SHORT 80-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:2,500 系列:- 類型:驅動器 驅動器/接收器數(shù):4/0 規(guī)程:RS422 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:16-SOIC N 包裝:帶卷 (TR) |
| IDT82P2281PFG8 | 功能描述:TXRX SGL T1/E1/J1 80-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82P2281PFGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Single T1/E1/J1 Long Haul / Short Haul Transceiver |
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