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參數(shù)資料
| 型號(hào)： | IDT74LVCH16601APVG8 |
| 廠(chǎng)商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 總線(xiàn)收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | GREEN, SSOP-56 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 84K |
| 代理商： | IDT74LVCH16601APVG8 |
INDUSTRIALTEMPERATURERANGE
IDT74LVCH16601A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
1
CLKAB
B1
OEAB
LEAB
LEBA
CLKENBA
54
1
56
55
2
28
30
29
27
3
CLKBA
OEBA
A1
CLKENAB
CE
1D
C1
CLK
CE
1D
C1
CLK
TO 17 OTHER CHANNELS
JUNE 2006
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2006 Integrated Device Technology, Inc.
DSC-4074/5
FEATURES:
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
μμμμμ W typ. static)
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in SSOP package
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
IDT74LVCH16601A
DESCRIPTION:
The LVCH16601A 18-bit universal bus transceiver is built using ad-
vanced dual metal CMOS technology. The LVCH16601A combines D-type
latches and D-type flip-flops to allow data flow in transparent, latched and
clocked modes.
Data flow in each direction is controlled by output-enable (
OEAB and
OEBA), latched-enable (LEAB and LEBA), and clock (CLKAB and CLKBA)
inputs. The clock can be controlled by the clock-enable (
CLKENAB and
CLKENBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at
a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/
flip-flop on the low-to-high transition of CLKAB. Output enable
OEABisactive
low. When
OEAB is low, the outputs are active. When OEAB is high, the
outputs are in the high-impedance state. Data flow for B to A is similar to that
of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVCH16601A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16601A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
3.3V CMOS 18-BIT
UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O, BUS-HOLD
相關(guān)PDF資料 |
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| IDT74LVCH16601APV | LVC/LCX/Z SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| IDT74LVCH16721APF8 | LVC/LCX/Z SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| IDT74LVCH16721APA | LVC/LCX/Z SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| IDT74LVCH16827APF8 | LVC/LCX/Z SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56 |
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