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參數(shù)資料
| 型號(hào)： | IDT74FCT2652ATQG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | QSOP-24 |
| 文件頁(yè)數(shù)： | 8/9頁(yè) |
| 文件大?。?/td> | 83K |
| 代理商： | IDT74FCT2652ATQG8 |
INDUSTRIALTEMPERATURERANGE
8
IDT74FCT2652AT/CT
FASTCMOSOCTALTRANSCEIVER/REGISTER(3-STATE)
Pulse
G enerator
R T
D.U.T.
V CC
V IN
C L
V OUT
50pF
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
IN PUT
TIM ING
INPUT
ASYNC HR O NOU S C ON TROL
PRES ET
C LEAR
ETC.
SYNCHRON OUS CONTROL
tSU
tH
tREM
tSU
tH
H IGH-LOW -HIG H
PULSE
LOW -H IGH -LOW
PULSE
tW
1.5V
SAM E PH ASE
IN PU T TR AN SITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE PH ASE
IN PU T TR AN SITION
3V
1.5V
0V
tPLH
tPHL
VOL
CONTROL
INPU T
3V
1.5V
0V
3.5V
0V
OUTPU T
NORM A LLY
LOW
OUTPU T
NORM A LLY
HIGH
SW ITCH
CLO SE D
SW ITC H
OPEN
VOL
0.3V
tPLZ
tPZL
tPZH
tPHZ
3.5V
0V
1.5V
EN AB LE
DISA BLE
VOH
PRES ET
C LEAR
CLOCK ENABLE
ETC.
Octal link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-Up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74FCT2652TQ | 制造商:Integrated Device Technology Inc 功能描述: |
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| IDT74FCT273ATSO | 制造商:Integrated Device Technology Inc 功能描述: |
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| IDT74FCT273P | 制造商:Integrated Device Technology Inc 功能描述: |
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