參數(shù)資料
型號: IDT74ALVCH162374PAG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/6頁
文件大?。?/td> 0K
描述: IC FLIP FLOP 16BIT D 3ST 48TSSOP
標(biāo)準(zhǔn)包裝: 39
系列: 74ALVCH
功能: 標(biāo)準(zhǔn)
類型: D 型
輸出類型: 三態(tài)非反相
元件數(shù): 2
每個(gè)元件的位元數(shù): 8
頻率 - 時(shí)鐘: 150MHz
延遲時(shí)間 - 傳輸: 1ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 12mA,12mA
電源電壓: 2.3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
包裝: 管件
其它名稱: 74ALVCH162374PAG
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH162374
3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP
1
JULY 2009
INDUSTRIAL TEMPERATURE RANGE
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
2009 Integrated Device Technology, Inc.
DSC-4565/5
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
μμμμμ W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in TSSOP package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
This 16-bit edge-triggered D-type flip-flop is built using advanced dual metal
CMOStechnology.TheALVCH162374isparticularlysuitableforimplementing
bufferregisters,I/Oports,bidirectionalbusdrivers,andworkingregisters.Itcan
be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of
the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up
atthedata(D)inputs.
OEcanbeusedtoplacetheeightoutputsineitheranormal
logic state (high or low logic levels) or a high-impedance state. In the high-
impedance state, the outputs neither load nor drive the bus lines significantly.
The high-impedance state and the increased drive provide the capability to
drive bus lines without need for interface or pullup components.
OE does not
affect internal operations of the flip-flop. Old data can be retained or new data
can be entered while the outputs are in the high-impedance state.
TheALVCH162374hasseriesresistorsinthedeviceoutputstructurewhich
will significantly reduce line noise when used with light loads. This driver has
been designed to drive ±12mA at the designated threshold levels.
The ALVCH162374 has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance.Thispreventsfloatinginputsand
eliminates the need for pull-up/down resistor.
DRIVE FEATURES:
Balanced Output Drivers: ±12mA
Low switching noise
IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-
TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
AND BUS-HOLD
1
OE
C1
1D
1
D1
47
1
CLK
1
Q1
TO 7 OTHER CHANNELS
2
OE
2
D1
36
2
CLK
2
Q1
TO 7 OTHER CHAN-
NELS
1
48
2
24
25
13
C1
1D
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
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