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參數(shù)資料
| 型號： | IDT7005L55PFB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 8K X 8 DUAL-PORT SRAM, 55 ns, PQFP64 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-64 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 189K |
| 代理商： | IDT7005L55PFB |
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
15
Waveform of Interrupt Timing(1)
Truth Table III — Interrupt Flag(1,4)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (
CE or R/W) asserted last.
4. Timing depends on which enable signal (
CE or R/W) is de-asserted first.
NOTES:
1. Assumes
BUSYL = BUSYR = VIH.
2. If
BUSYL = VIL, then no change.
3. If
BUSYR = VIL, then no change.
4.
INTR and INTL must be initialized at power-up.
2738 drw 17
ADDR"A"
INTERRUPT SET ADDRESS
(2)
CE"A"
R/
W"A"
tAS
(3)
tWC
tWR
(4)
tINS
(3)
INT"B"
2738 drw 18
ADDR"B"
INTERRUPT CLEAR ADDRESS
(2)
CE"B"
OE"B"
tAS
(3)
tRC
tINR
(3)
INT"B"
Left Port
Right Port
Function
R/
WL
CEL
OEL
A12L-A0L
INTL
R/
WR
CER
OER
A12R-A0R
INTR
LL
X
1FFF
X
L(2)
Set Right
INTR Flag
X
XXX
X
L
1FFF
H(3)
Reset Right
INTR Flag
XX
X
L(3)
L
X
1FFE
X
Set Left
INTL Flag
XL
L
1FFE
H(2)
X
Reset Left
INTL Flag
2738 tbl 17
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相關(guān)代理商/技術(shù)參數(shù) |
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| IDT7005L55XL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| IDT7005L55XLB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| IDT7005L70F | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT7005L70FB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT7005L70G | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
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