參數(shù)資料
型號(hào): IDT7005L55GB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: Single, Ultra Low Cost, RRIO CMOS Amplifier
中文描述: 8K X 8 DUAL-PORT SRAM, 55 ns, CPGA68
封裝: 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-68
文件頁(yè)數(shù): 12/20頁(yè)
文件大?。?/td> 189K
代理商: IDT7005L55GB
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
2
Description
The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM. The
IDT7005 is designed to be used as a stand-alone 64K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
wordsystems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproach
in 16-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power. Low-power (L)
versions offer battery backup data retention capability with typical power
consumption of 500W from a 2V battery.
The IDT7005 is packaged in a ceramic 68-pin PGA, 68-pin quad
flatpack, 68-pin PLCC and a 64-pin thin quad flatpack, (TQFP). Military
gradeproductismanufacturedincompliancewiththelatestrevisionofMIL-
PRF-38535 QML making it ideally suited to military temperature applica-
tions demanding the highest level of performance and reliability.
Pin Configurations(1,2,3)
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .12 in.
F68-1 package body is approximately .97 in x .97 in x .08 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking
2738 drw 02
12
13
14
15
16
17
18
INDEX
19
20
21
22
987
6
5
4
3
21 68 67 66 65
27 28 29 30 31 32 33 34 35 36 37 38 39
V
C
VCC
I/O1R
I/O2R
I/O3R
I/O4R
INTL
GND
A4L
A3L
A2L
A1L
A0L
A3R
A0R
A1R
A2R
I/O2L
A5L
R
/W
L
11
10
M/S
23
24
25
26
40 41 42 43
58
57
56
55
54
53
52
51
50
49
48
59
60
47
46
45
44
64 63 62 61
I/O3L
GND
I/O0R
VCC
A4R
BUSYL
GND
BUSYR
INTR
A
1
2
R
I/
O
7
R
N
/C
G
N
D
O
E
R
/W
R
S
E
M
R
C
E
R
O
E
L
S
E
M
L
C
E
L
N
/C
I/
O
0
L
I/
O
1
L
IDT7005J or F
J68-1(4)
F68-1(4)
68 Pin PLCC / FLATPACK
Top View(5)
I/O4L
I/O5L
I/O6L
I/O7L
I/O5R
I/O6R
N
/C
A
1
2
L
N
/C
A
1
R
N
/C
A
1
0
R
A
9
R
A
8
R
A
7
R
A
6
R
A
5
R
A
1
L
A
1
0
L
A
9
L
A
8
L
A
7
L
A
6
L
N
/C
,
11/16/01
INDEX
7005PF
PN-64(4)
64-Pin TQFP
Top View(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
1
7
1
8
1
9
2
0
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
1
4
9
5
0
5
1
5
2
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
4
5
3
6
4
I/O2L
VCC
GND
A4R
BUSYL
BUSYR
INTR
INTL
GND
M/
S
O
E
L
A
5
L
I/
O
1
L
R
/W
L
C
E
L
S
E
M
L
V
C
N
/C
N
/C
O
E
R
C
E
R
/W
R
S
E
M
R
A
1
2
R
G
N
D
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/
O
6
R
I/
O
7
R
A
1
R
A
1
0
R
A
9
R
A
8
R
A
7
R
A
6
R
A
5
R
A3R
A2R
A1R
A0R
A0L
A1L
A2L
A3L
A4L
A
6
L
A
7
L
A
8
L
A
9
L
A
1
0
L
A
1
L
A
1
2
L
I/
O
0
L
2738 drw 03
.
11/16/01
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