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參數(shù)資料
| 型號(hào)： | IDT5V49EE902NLGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 19/33頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PLL 500MHZ 32VFQFPN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS，LVDS，LVPECL，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:7 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-VFQFPN（5x5） |
| 包裝： | 托盤 |
| 其它名稱： | 800-2582 |
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IDT5V49EE902
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
26
IDT5V49EE902
REV P 092412
0x56
00
IP3[3:0]_CFG4
RZ3[3:0]_CFG4
PLL3 Loop Parameter
0x57
00
IP3[3:0]_CFG5
RZ3[3:0]_CFG5
0x58
00
IP3[3:0]_CFG0
RZ3[3:0]_CFG0
0x59
00
IP3[3:0]_CFG1
RZ3[3:0]_CFG1
0x5A
00
IP3[3:0]_CFG2
RZ3[3:0]_CFG2
0x5B
00
IP3[3:0]_CFG3
RZ3[3:0]_CFG3
0x5C
03
Reserved
D3[6:0]_CFG0
PLL3 Reference Divide and input
sel
D3[6:0] - 127 step Ref Div
D3 = 0 means power down.
0x5D
03
Reserved
D3[6:0]_CFG1
0x5E
03
Reserved
D3[6:0]_CFG2
0x5F
03
Reserved
D3[6:0]_CFG3
0x60
03
Reserved
D3[6:0]_CFG4
0x61
03
Reserved
D3[6:0]_CFG5
0x62
0C
N3[7:0]_CFG4
N - Feedback Divider
12 - 4095 (values of “0” through
“11” are not allowed)
0x63
0C
N3[7:0]_CFG5
0x64
0C
N3[7:0]_CFG0
0x65
0C
N3[7:0]_CFG1
0x66
0C
N3[7:0]_CFG2
0x67
0C
N3[7:0]_CFG3
0x68
00
SSVCO[7:0]_CFG0
SSVCO[7:0] - PLL3 Spread
Spectrum Loop Feedback
Counter
See Addr 0x80:0x85 for
SSVCO[15:8]
0x69
00
SSVCO[7:0]_CFG1
0x6A
00
SSVCO[7:0]_CFG2
0x6B
00
SSVCO[7:0]_CFG3
0x6C
00
SSVCO[7:0]_CFG4
0x6D
00
SSVCO[7:0]_CFG5
0x6E
00
SS_D3[7:0]_CFG4
SS_D[7:0] - PLL3 Spread
Spectrum Reference Divide
0x6F
00
SS_D3[7:0]_CFG5
0x70
00
SS_D3[7:0]_CFG0
0x71
00
SS_D3[7:0]_CFG1
0x72
00
SS_D3[7:0]_CFG2
0x73
00
SS_D3[7:0]_CFG3
0x74
01
Reserved
0x75
03
OEM0[1:0]
SLEW0[1:0]
INV0
Reserved
S1
S3
Output Controls
S1=1 - OUT1/OUT2 are from
DIV1/DIV2 respectively
S1=0 - Both from DIV2
S3 =1 - OUT3/OUT6 are from
DIV3/DIV6
S3=0 - Both from DIV6
SLEW# - LVTTL only
OEM#–output enable mode
x0 - tristated
01 - park low
11 - park high
OEM0 controls OUT0 only
0x76
00
OEM1[1:0]
SLEW1[1:0]
INV1[1:0]
LVL1[1:0]
Output Controls
LVL1[1:0] - output pair 2:1 if
selected
[00] - LVTTL
[01] - LVDS
[10] - LVPECL
[11] - HCSL
INV1 [CLK1, CLK2]
[0] - normal
[1] - invert clock
OEM1 controls OUT1/OUT2
Addr
Default
Register
Hex
Value
Bit #
Description
76
5
4
3
2
1
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V49EE902NLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 32QFN |
| IDT5V49EE903NLGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GENERATOR |
| IDT5V49EE903NLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 32QFN |
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