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參數(shù)資料
| 型號： | ICS9160M-03 |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO32 |
| 封裝： | SOIC-32 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 240K |
| 代理商： | ICS9160M-03 |
2
ICS9160-03
Preliminary Product Preview
Pin Descriptions
* Frequencies assuming an input or crystal of 14.318 MHz.
** Device provides 18pF load capacitance for crystal.
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
2X1
IN
XTAL or external reference frequency input. This input includes XTAL load
capacitance and feedback bias for a 10-30 MHz XTAL.**
3
X2
OUT
XTAL output which includes XTAL load capacitance.**
1
4
VDDX
GNDX
PWR
XTAL oscillator circuit and REFCLK output power supplies.
5, 6, 7
FS(0:2)
IN
Frequency selection address pins. These inputs have pull-ups.
8, 9, 11, 12
PCLK(0:3)
OUT
Processor clock outputs which are a multiple of the input reference frequency as
shown in the table below.
10, 17
13
VDDP
GNDP
PWR
PCLK power supplies. VDDP powers the internal PCLK PLL and the
PCLK(0:3) outputs.
14
SDATA
IN
Serial stop clock data is clocked in on the falling edge of BCLK. A total of 15 bits
must be clocked in using the following protocol. SDATA is sampled on the falling
edge of BCLK, so the data generator should change data on the rising edge of
BCLK to ensure proper communication. SDATA must be low for one BCLK period
as a start bit. The next 15 rising edges of BCLK will clock data in serially. The
16th clock enables the serial data to take effect. Outputs associated with serial data
bits that are a one will continue without interruption. Clocks associated with serial
data bits that are a zero will be stopped in the low state glitch-free, that is, no short
clocks with the exception of REFCLK and KEYBD which do not stop. This input
has an internal pull-up device.
15, 16
STOP(0:1)
IN
Stop clock control pins used for glitch-free start and stop of the clock outputs as
described in the table on the next page. These inputs have internal pull-up devices.
18
REFCLK
OUT
Buffered copy of the crystal reference frequency.
19, 21, 22, 24,
25, 27, 28
BCLK(0:6)
OUT
Bus clock outputs having selectable frequency based on the FS(0:2) inputs (see
table on next page).
20
23
GNDB
VDDB
PWR
BCLK power supplies. VSSB and VDDB power BCLK(0:6).
26
29
GNDF
VDDF
PWR
Fixed clock power supplies. VSSF and VDDF power GRAPHIC, FLOPPY and
KEYBD outputs plus the fixed clock PLL.
30
FLOPPY
OUT
The floppy clock output operates at 24 MHz..*
31
KEYBD
OUT
The keyboard clock output operates at 12 MHz.*
32
GRAPHIC
OUT
The graphics system clock output operates at 40 MHz.*
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