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參數(shù)資料
| 型號： | ICS91309YM-T |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 106K |
| 代理商： | ICS91309YM-T |
4
ICS91309
0093G—02/11/04
Electrical Characteristics - Outputs
TA = 0 - 70°C; VDD = 3.3 V +/-10%; CL = 30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
VOH
IOH = -12 mA
2.4
V
Output Low Voltage
VOL
IOL = 12 mA
0.4
V
Rise Time
1
tr
Measure between 0.8 V and 2.0 V
1.2
1.5
ns
Fall Time
1
tf
Measure between 2.0 V and 0.8 V
1.2
1.5
ns
PLL Lock Time
1
TLOCK
Stable VDD, valid clock on REF
1mS
f1
CL = 30 pF
10
100
MHz
f1
CL = 10 pF
10
133
MHz
Dt1
Measured at 1.4 V, Fout = 66.7 MHz
40
50
60
%
Dt2
Measured at VDD/2, Fout < 50.0 MHz
45
50
55
%
Jitter, Cycle-to-cycle
1
tjcyc-cyc
Measured at 66.7 MHz, loaded outputs
125
ps
Jitter, Absolute
1
Tjabs
10,000 cycles, CL = 30 pF
-100
70
100
ps
Jitter, 1-Sigma
1
Tj1s
10,000 cycles, CL = 30 pF
14
30
ps
Skew, Group-to-Group
1
Tsk
Measured at 1.4 V
215
ps
Skew, Output-to-Output
1
Tsk
Measured at 1.4 V, within a group
100
ps
Skew, Device-to-Device
1
Tdsk-Tdsk Measured at VDD/2,on CLKOUT pins
700
ps
Delay, Input-to-Output
1
Dr1
Measured at 1.4 V
700
ps
Notes:
1. Guaranteed by design and characterization, not 100% tested in production.
Duty Cycle
1
Output Frequency
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