- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄65534 > ICS9147F-08LF 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 PDF資料下載
參數(shù)資料
| 型號(hào)： | ICS9147F-08LF |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 272K |
| 代理商： | ICS9147F-08LF |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9147- 08
Block Diagram
Pentium is a trademark of Intel Corporation
Frequency Generator & Integrated Buffers for 686 Series CPUs
9147-08RevA060497P
Pin Configuration
The ICS9147-08 generates all clocks required for high
speed RISC or CISC microprocessor systems such as Intel
Pentium and PentiumPro, AMD or Cyrix processors. Three
bidirectional
I/O pins (FS0, FS1, BSEL) are latched at
power-on to the functionality table. The Six BUS clocks
can be selected as either synchronous at 1/2 CPU speed or
asynchronous at 34.3MHz selected by BSEL latched
input.The inputs provide for test mode conditions to aid in
system level testing. An output enable pin tristates all
outputs for system testing. The slow clock mode will
transition the CPU, SDRAM and PCI clocks from 60 or 66.6
MHz CPU to half speed when SLOW# input is low.
High drive BUS and SDRAM outputs typically provide greater
than 1V/ns slew rate into 30 pF loads. CPU outputs typically
provide better than 1V/ns slew rate into 20 pF loads while
maintaining 50±5% duty cycle. The REF clock outputs
typically provide better than 0.5V/ns slew rates. Seperate
buffer supply pin VDDL allows for nominal 3.3V voltage
or reduced voltage swing (from 2.9 to 2.5V) for CPUL (1:2)
and IOAPIC outputs.
Total of 15 CPU speed clocks:
- Two copies of CPU clock with VDDL (2.5 to 3.3V)
- Twelve (12) SDRAM (3.3v) plus one
CPUH (3.3V) clocks
Six copies of PCI clock (synchronous with CPU clock/2 or
asynchronous 34.3 MHz)
Slow clock mode ramps CPU PLL to half speed (from 60
or 66.6 MHz)
250ps output skew window for CPU andSDRAM clocks
and 500ps window BUS clocks.
CPU clocks to BUS clocks skew 1-3ns (CPU early)
Two copies of Ref. clock @14.31818 MHz (One driven by
VDDL as IOAPIC)
One 48 MHz (3.3 V TTL) for USB support and single
20 MHz for Data Communications
±100PPM Freq accuracy with better than: ±30PPM initial
XTAL accuracy, and ±70PPM due to temp , aging and
load CAP variation.
Separate VDDL for CPUL (1:2) clock buffers and IOAPIC
to allow 2.5V output (or Std. Vdd)
3.0V – 3.7V supply range w/2.5V compatible outputs
48-pin SSOP package
48-Pin SSOP
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS9147F-PPP-LF | 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9147F-22 | 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148M-60LF | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| ICS9148F-60LF | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| ICS9158-05M | 66.7 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9147F-08T | 制造商:ICS 功能描述: |
| ICS9147F-09 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for 686 Series CPUs |
| ICS9147F-12 | 制造商:ICS 制造商全稱:ICS 功能描述:Pentium/ProTM System and Cyrix⑩ Clock Chip |
| ICS9147F-14 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9147F-16 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUMTM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。