參數(shù)資料
型號: ICS853111BY-02
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, 1 MM HEIGHT, TQFP-32
文件頁數(shù): 8/10頁
文件大?。?/td> 151K
代理商: ICS853111BY-02
853111BY-02
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 27, 2003
7
Integrated
Circuit
Systems, Inc.
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PRELIMINARY
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
F
OUT
F
IN
5
2 Zo
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o = 50
Z
o = 50
RTT =
1
(V
OH + VOL / VCC –2) –2
Z
o
Z
o = 50
Z
o = 50
50
50
RTT
V
CC - 2V
F
IN
F
OUT
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FIGURE 3B. LVPECL OUTPUT TERMINATION
FIGURE 3A. LVPECL OUTPUT TERMINATION
Figure 2 shows an example of the differential input that can
be wired to accept single ended levels. The reference voltage
level V
BB generated from the device is connected to the
CLK_IN
C1
0.1uF
VDD(or VCC)
+
-
VBB
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
negative input. The C1 capacitor should be located as close
as possible to the input pin.
TERMINATION FOR LVPECL OUTPUTS
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