參數(shù)資料
型號(hào): ICS86004AG-02
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 86004 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝: 4.40 X 5 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16
文件頁數(shù): 1/10頁
文件大?。?/td> 580K
代理商: ICS86004AG-02
62.5MHZ TO 250MHZ, 1-TO-4 LVCMOS/
LVTTL ZERO DELAY CLOCK BUFFER
ICS86004-02
IDT / ICS LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
1
ICS86004AG-02 REV A NOVEMBER 3, 2006
PRELIMINARY
GENERAL DESCRIPTION
The ICS86004-02 is a high performance 1-to-4
LVCMOS/LVTTL Clock Buffer and a member of
the HiPerClockSfamily of High Performance Clock
Solutions from IDT. The ICS86004-02 has a fully
integrated PLL and can be configured as zero
delay buffer and has an input and output frequency range of
62.5MHz to 250MHz. The external feedback allows the device
to achieve “zero delay” between the input clock and the output
clocks. The PLL_SEL pin can be used to bypass the PLL for
system test and debug purposes. In bypass mode, the refer-
ence clock is routed around the PLL and into the internal out-
put divider.
ICS86004-02 has a special feature that when CLK is LOST, it
will disable the output to logic LOW.
FEATURES
Four LVCMOS/LVTTL outputs, 7
typical output impedance
Single LVCMOS/LVTTL clock input
CLK accepts the following input levels: LVCMOS or LVTTL
Output frequency range: 62.5MHz to 250MHz
Input frequency range: 62.5MHz to 250MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Fully integrated PLL
Cycle-to-cycle jitter, (F_SEL = 1): 35ps (typical)
Output skew: 45ps (typical)
Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
5V tolerant input
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
compliant packages
HiPerClockS
ICS
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL_SEL
CLK
FB_IN
MR
F_SEL
Q0
Q1
Q2
Q3
Q1
GND
Q0
F_SEL
VDD
CLK
GND
VDDA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDO
Q2
GND
Q3
VDDO
MR
FB_IN
PLL_SEL
ICS86004-02
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
CONTROL INPUT FUNCTION TABLE
t
u
p
n
I
t
u
p
t
u
O
/
t
u
p
n
I
)
z
H
M
(
e
g
n
a
R
y
c
n
e
u
q
e
r
F
L
E
S
_
Fm
u
m
i
n
i
Mm
u
m
i
x
a
M
05
2
10
5
2
15
.
2
65
2
1
PLL
1:1
÷8
0
1
0
1
LOSS Reference Detect
Pulldown
Pullup
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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