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參數(shù)資料
| 型號： | ICS726ATLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VCXO 3.3V 12-36MHZ 6-TSOT |
| 標準包裝： | 2,500 |
| 類型： | 壓控晶體振蕩器（VCXO） |
| PLL： | 無 |
| 輸入： | 晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 36MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 細型，TSOT-23-6 |
| 供應商設備封裝： | TSOT-23-6 |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 726ATLFT |
ICS726A
12 TO 36 MHZ 6TSOT VCXO
VCXO
IDT 12 TO 36 MHZ 6TSOT VCXO
3
ICS726A
REV E 021312
The third overtone mode of the crystal and all spurs must be
>100 ppm distant from the 3x fundamental resonance
measured with a physical load of 8.6pF.
The external crystal must be connected as close to the chip
as possible and should be on the same side of the PCB as
the ICS726A. There should be no vias between the crystal
pins and the X1 and X2 device pins. There should be no
signal traces underneath or close to the crystal. See
application note MAN05.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture and
frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the value of the crystal capacitors:
1. Connect VDD of the ICS726A to 3.3 V. Connect pin 5of
the ICS726A to the second power supply. Adjust thevoltage
on pin 5 to 0V. Measure and record the frequency ofthe CLK
output. (f0V)
2. Adjust the voltage on pin 5 to 3.3 V. Measure and record
the frequency of the same output. (fhigh)
Errorxtal = actual initial accuracy (in ppm) of the crystal being
measured.
If the centering error is less than ±25 ppm, no adjustment is
needed. If the centering error is more than 25 ppm negative,
the PC board has excessive stray capacitance and a new
PCB layout should be considered to reduce stray
capacitance. (Alternately, the crystal may be re-specified to
a higher load capacitance. Contact IDT for details.) If the
centering error is more than 25 ppm positive, add identical
fixed centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
= 2 x (centering error)/ (trim sensitivity)
Trim sensitivity is a parameter which can be supplied by your
crystal vendor or calculated using the following formula:
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS726T | 制造商:ICS 制造商全稱:ICS 功能描述:12 TO 36 MHZ SOT-23 VCXO |
| ICS726TLF | 制造商:ICS 制造商全稱:ICS 功能描述:12 TO 36 MHZ SOT-23 VCXO |
| ICS726TLFT | 功能描述:IC VCXO 3.3V 12-36MHZ 6-TSOT RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS726TT | 功能描述:IC VCXO 3.3V 12-36MHZ 6-TSOT RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS728 | 制造商:ICS 制造商全稱:ICS 功能描述:LOW COST 27 MHZ 3.3 VOLT VCXO |
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