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參數(shù)資料
| 型號： | ICS663MT |
| 英文描述： | PLL BUILDING BLOCK |
| 中文描述： | 鎖相環(huán)積木 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大小： | 146K |
| 代理商： | ICS663MT |
PLL B
UILDING
B
LOCK
MDS 663 D
5
Revision 062904
Integrated Circuit Systems
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
ICS663
External Components
The ICS663 requires a minimum number of external
components for proper operation. A decoupling
capacitor of 0.01
μ
F should be connected between VDD
and GND as close to the ICS663 as possible. A series
termination resistor of 33
may be used at the clock
output.
Special considerations must be made in choosing loop
components C
1
and C
2
:
1) The loop capacitors should be a low-leakage type to
avoid leakage-induced phase noise. For this reason,
DO NOT use any type of polarized or electrolytic
capacitors.
2) Microphonics (mechanical board vibration) can also
induce output phase noise when the loop bandwidth is
less than 1 kHz. For this reason, ceramic capacitors
should have C0G or NP0 dielectric. Avoid high-K
dielectrics like Z5U and X7R. These and some other
ceramics have piezoelectric properties that convert
mechanical vibration into voltage noise that interferes
with VCXO operation.
For larger loop capacitor values such as 0.1
μ
F or 1
μ
F,
PPS film types made by Panasonic, or metal poly types
made by Murata or Cornell Dubilier are recommended.
For questions or changes regarding loop filter
characteristics, please contact your sales area FAE, or
ICS Applications.
Figure 1. Example Configuration
-- Generating a 20 MHz clock from a 200 kHz reference
Avoiding PLL Lockup
In some applications, the ICS663 can “l(fā)ock up” at the
maximum VCO frequency. The way to avoid this
problem is to use an external divider that always
operates correctly regardless of the CLK output
frequency. The CLK output frequency may be up to 2x
the maximum Output Clock Frequency listed in the AC
Electrical Characteristics above when the device is in
an unlocked condition. Make sure that the external
divider can operate up to this frequency.
Explanation of Operation
The ICS663 is a PLL building block circuit that includes
an integrated VCO with a wide operating range. The
device uses external PLL loop filter components which
through proper configuration allow for low input clock
reference frequencies, such as a 15.7 kHz Hsync input.
The phase/frequency detector compares the falling
edges of the clocks inputted to FBIN and REFIN. It then
generates an error signal to the charge pump, which
produces a charge proportional to this error. The
external loop filter integrates this charge, producing a
voltage that then controls the frequency of the VCO.
This process continues until the edges of FBIN are
aligned with the edges of the REFIN clock, at which
point the output frequency will be locked to the input
frequency.
REFIN
+3.3 or 5 V
VDD
SEL
0.01
μ
F
FBIN
200 kHz
100
Digital Divider such as
ICS674-01
GND
CLK
LFR
20 MHz
LF
C
1
R
Z
C
2
200 kHz
ICS663
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS664-01 | Digital Video Clock Source |
| ICS664G-01 | Digital Video Clock Source |
| ICS664G-01T | Digital Video Clock Source |
| ICS664-02 | PECL Digital Video Clock Source |
| ICS664G-02TR | PECL Digital Video Clock Source |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS664-01 | 制造商:ICS 制造商全稱:ICS 功能描述:Digital Video Clock Source |
| ICS664-02 | 制造商:ICS 制造商全稱:ICS 功能描述:PECL Digital Video Clock Source |
| ICS664-03 | 制造商:ICS 制造商全稱:ICS 功能描述:Digital Video Clock Source |
| ICS664-03LF | 制造商:ICS 制造商全稱:ICS 功能描述:Digital Video Clock Source |
| ICS664-03LFT | 制造商:ICS 制造商全稱:ICS 功能描述:Digital Video Clock Source |
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