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參數(shù)資料
| 型號(hào)： | ICS663MT |
| 英文描述： | PLL BUILDING BLOCK |
| 中文描述： | 鎖相環(huán)積木 |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 146K |
| 代理商： | ICS663MT |
PLL B
UILDING
B
LOCK
MDS 663 D
2
Revision 062904
Integrated Circuit Systems
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
ICS663
Pin Assignment
VCO Post Divide Select Table
0 = connect pin directly to ground
1 = connect pin directly to VDD
Pin Descriptions
1
2
3
FBIN
4
VDD
GND
CLK
LF
SEL
LFR
8
7
6
5
REFIN
8 Pin (150 mil) SOIC
SEL
VCO Post
Divide
8
2
0
1
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
FBIN
Input
Feedback clock input. Connect the output of the feedback divider to
this pin. Falling edge triggered.
2
VDD
Power
VDD. Connect to +3.3 V or +5 V.
3
GND
Power
Connect to ground.
4
LF
Input
Loop filter connection (refer to Figure 1 on Page 5).
When using the phase detector block only, this pin serves as the
charge pump output.
When using the VCO block only, this pin serves as VCO input control
voltage.
5
LFR
Input
Loop filter return (refer to Figure 1 on Page 5).
6
SEL
Input
Select pin for VCO post divide, as per above table.
7
CLK
Output
Clock output.
8
REFIN
Input
Reference clock input. Connect the input clock to this pin. Falling edge
triggered.
相關(guān)PDF資料 |
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| ICS664-01 | Digital Video Clock Source |
| ICS664G-01 | Digital Video Clock Source |
| ICS664G-01T | Digital Video Clock Source |
| ICS664-02 | PECL Digital Video Clock Source |
| ICS664G-02TR | PECL Digital Video Clock Source |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS664-01 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Digital Video Clock Source |
| ICS664-02 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:PECL Digital Video Clock Source |
| ICS664-03 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Digital Video Clock Source |
| ICS664-03LF | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Digital Video Clock Source |
| ICS664-03LFT | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Digital Video Clock Source |
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