參數(shù)資料
型號(hào): ICS1893BKILFT
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 81/133頁(yè)
文件大?。?/td> 0K
描述: PHYCEIVER LOW PWR 3.3V 56-VQFN
標(biāo)準(zhǔn)包裝: 1
系列: PHYceiver™
類(lèi)型: PHY 收發(fā)器
規(guī)程: MII
電源電壓: 3.14 V ~ 3.47 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 56-VFQFP-EP(8x8)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 1252 (CN2011-ZH PDF)
其它名稱(chēng): 800-1795-6
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)當(dāng)前第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)
Chapter 7 Management Register Set
ICS1893BF, Rev. F, 5/13/10
May, 2010
51
ICS1893BF Data Sheet Rev. F - Release
Copyright 2009, IDT, Inc.
All rights reserved.
7.1.2 Management Register Bit Access
The ICS1893BF Management Registers include one or more of the following types of bits:
7.1.3 Management Register Bit Default Values
The tables in this chapter specify for each register bit the default value, if one exists. The ICS1893BF sets
all Management Register bits to their default values after a reset. Table 7-4 lists the valid default values for
ICS1893BF Management Register bits.
Note: The ICS1893BF has a number of reserved bits throughout the Management Registers. Most of
these bits provide enhanced test modes. The Management Register tables provide the default
values for these bits. The STA must not change the value of these bits under any circumstance. If
the STA inadvertently changes the default values of these reserved register bits, normal operation
of the ICS1893BF can be affected.
Table 7-3. Description of Management Register Bit Types
Management
Register Bit Types
Bit
Symbol
Description
Read-Only
RO
An STA can obtain the value of a RO register bit. However, it cannot
alter the value of (that is, it cannot write to) an RO register bit. The
ICS1893BF isolates any STA attempt to write a value to an RO bit.
Command Override
Write
CW
An STA can read a value from a CW register bit. However, write
operations are conditional, based on the value of the Command
Register Override bit (bit 16.15). When bit 16.15 is logic:
Zero (the default), the ICS1893BF isolates STA attempts to write to
the CW bits (that is, CW bits cannot be altered when bit 16.15 is
logic zero).
One, the ICS1893BF permits an STA to alter the value of the CW
bits in the subsequent register write. (Bit 16.15 is self-clearing and
automatically clears to zero on the subsequent write.)
Read/Write
R/W
An STA can unconditionally read from or write to a R/W register bit.
Read/Write Zero
R/W0
An STA can unconditionally read from a R/W0 register bit, but only a
‘0’ value can be written to this bit.
Table 7-4. Range of Possible Valid Default Values for ICS1893BF Register Bits
Default Condition
Default Value
Indicates there is no default value for the bit
0
Indicates the bit’s default value is logic zero
1
Indicates the bit’s default value is logic one
State of pin at reset
For some bits, the default value depends on the state (that is, the logic value) of a
particular pin at reset (that is, the logic value of a pin is latched at reset). An
example of pins that have a default condition that depends on the state of the pin
at reset are the PHY / LED pins (P0AC, P1CL, P2LI, P3TD, and P4RD) discussed
in the following sections:
相關(guān)PDF資料
PDF描述
ADV7180BST48Z IC VID DECOD SDTV 10BIT 48LQFP
AD9889BBBCZ-80 TRANSMITTER HDMI/DVI 76-CSPBGA
AD8325ARUZ IC LN DVR CATV FINE-STEP 28TSSOP
MAX3430EPA+ IC TXRX RS-485 3.3V 8-DIP
VI-BWM-IV-F3 CONVERTER MOD DC/DC 10V 150W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS1893BKIT 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器,接收器,收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893BKLF 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器,接收器,收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893BKLFT 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器,接收器,收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893BKT 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器,接收器,收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893BRIEF 制造商:ICS 制造商全稱(chēng):ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver