參數(shù)資料
型號： ICS1893BFILF
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 82/133頁
文件大?。?/td> 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
標準包裝： 30
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 管件
其它名稱： 1893BFILF
ICS1893BF, Rev. F, 5/13/10
May, 2010
52
Chapter 7 Management Register Set
ICS1893BF Data Sheet - Release
Copyright 2009, IDT, Inc.
All rights reserved.
7.1.4 Management Register Bit Special Functions
This section discusses the types of special functions for the Management Register bits.
7.1.4.1 Latching High Bits
The purpose of a latching high (LH) bit is to record an event. An LH bit records an event by monitoring an
active-high signal and then latching this active-high signal when it triggers (that is, when the event occurs).
A latching high bit, once set to logic one, remains set until either a reset occurs or it is read by an STA.
Immediately following an STA read of an LH bit, the ICS1893BF latches the current state of the signal into
the LH bit. When an STA reads an LH bit:
Once, the LL bit provides the STA with a history of whether or not the event has ever occurred. That is,
this first read provides the STA with a history of the condition and latches the current state of the signal
into the LL bit for the next read.
Twice in succession, the LH bit provides the STA with the current state of the monitored signal.
7.1.4.2 Latching Low Bits
As with latching high bits, the purpose of a latching low (LL) bit is also to record an event. An LL bit records
an event by monitoring an active-low signal and then latching this active-low signal when it triggers (that is,
when the event occurs).
A latching low bit, once cleared to logic zero, remains cleared until either a reset occurs or it is read by an
STA. Immediately following an STA read of an LL bit, the ICS1893BF latches the current state of the
active-low signal into the LL bit. When an STA reads an LL bit:
Once, the LL bit provides the STA with a history of whether or not the event has ever occurred. That is,
this first read provides the STA with a history of the condition and latches the current state of the signal
into the LL bit for the next read.
Twice in succession, the LL bit provides the STA with the current state of the monitored signal.
7.1.4.3 Latching Maximum Bits
For the ICS1893BF, the purpose of latching maximum (LMX) bits is to track the progress of internal state
machines. The LMX bits act in combination with other LMX bits to save the maximum collective value of a
defined group of LMX bits, from the most-significant bit to the least-significant bit.
For example, assume a group of LMX bits is defined as register bits 13 through 11. If these bits first have a
value of 3o (octal) and then the state machine they are monitoring advances to state:
2o, then the 2o value does not get latched.
4o (or any other value greater than 3o), then in this case, the value of 4o does get latched.
LMX bits retain their value until either a reset occurs or they are read by an STA. Immediately following an
STA read of a defined group of LMX bits, the ICS1893BF latches the current state of the monitored state
machine into the LMX bits. When an STA reads a group of LMX bits:
Once, the LMX bits provide the STA with a history of the maximum value that the state machine has
achieved and latches the current state of the state machine into the LMX bits for the next read.
Twice in succession, the LMX bits provide the STA with the current state of the monitored state machine.
7.1.4.4 Self-Clearing Bits
Self-clearing (SC) bits automatically clear themselves to logic zero after a pre-determined amount of time
without any further STA access. The SC bits have a default value of logic zero and are triggers to begin
execution of a function. When the STA writes a logic one to an SC bit, the ICS1893BF begins executing the
function assigned to that bit. After the ICS1893BF completes executing the function, it clears the bit to
indicate that the action is complete.
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參數(shù)描述
ICS1893BFILFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893BFIT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
ICS1893BFLF 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893BFLFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
ICS1893BFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
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