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參數(shù)資料
| 型號(hào)： | ICS1893AFILF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 109/136頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | PHYceiver™ |
| 類型： | PHY 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 管件 |
| 其它名稱： | 1893AFILF |
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ICS1893AF, Rev D 10/26/04
October, 2004
74
Chapter 8
Management Register Set
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.6.5
Technology Ability Field (bits 4.9:5)
When its Auto-Negotiation sublayer is enabled, the ICS1893AF transmits its link capabilities to its remote
link partner during the auto-negotiation process. The Technology Ability Field (TAF) bits 4.12:5 determine
the specific abilities that the ICS1893AF advertises. The ISO/IEC specification defines the TAF
technologies in Annex 28B.
The ISO/IEC specification reserves bits 4.12:10 for future use. When each of these reserved bits is:
Read by an STA, the ICS1893AF returns a logic zero
Written to by an STA, the STA must use the default value specified in this data sheet
ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893AF,
an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA always write
the default value of any reserved bits during all management register write operations.
Reserved bits 4.12:10 are Command Override Write (CW) bits. Whenever bit 16.15 (the Command
Register Override bit) is logic:
Zero, the ICS1893AF isolates all STA writes to CW bits, including bits 4.12:10.
One, an STA can modify the value of bits 4.12:10
Each of the bits 4.9:5 in the TAF represent a specific technology capability. When one of these bits is logic:
Zero, it indicates to the remote link partner that the local device cannot support the technology
represented by the bit.
One, it indicates to the remote link partner that the local device can support the technology.
With the exception of bit 4.9, the default settings of the TAF bits depend on the ICS1893AF operating
mode. Bit 4.9 is always logic zero, indicating that the ICS1893AF cannot support 100Base-T4 operations.
The TAF bits are Command Override Write bits. The default value of these bits depends on the signal level
on the HW/SW pin and whether the Auto-Negotiation sublayer is enabled.
With the Auto-Negotiation Enable bit (bit 0.12) set to logic:
Zero (that is, disabled), the ICS1893AF does not execute the auto-negotiation process. Upon completion
of the initialization sequence, the ICS1893AF proceeds to the Idle state and begins transmitting IDLES.
Two Control Register bits – the Data Rate Select bit (bit 0.13) and the Duplex Select bit (bit 0.8) –
determine the technology mode that the ICS1893AF uses for data transmission and reception. In this
mode, the values of the TAF bits (bits 4.8:5) are undefined.
One (that is, enabled), the ICS1893AF executes the auto-negotiation process and advertises its
capabilities to the remote link partner. The TAF bits (bits 4.8:5) determine the capabilities that the
ICS1893AF advertises to its remote link partner. For the ICS1893AF, all of these bits 4.8:5 are set to
logic one, indicating the ability of the ICS1893AF to provide these technologies.
Note:
1.
The ICS1893AF does not alter the value of the Status Register bits based on the TAF bits in
register 4, as the ISO/IEC definitions for the Status Register bits require these bits to indicate all the
capabilities of the ICS1893AF.
2.
The STA can alter the default TAF bit settings, 4.12:5, and subsequently issue an Auto-Negotiation
Restart.
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| ICS1893AFILFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893AFIT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AFLF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):1/1 規(guī)程:RS422，RS485 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOICN 包裝:剪切帶 (CT) 其它名稱:ISL31470EIBZ-T7ACT |
| ICS1893AFLFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893AFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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