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參數(shù)資料
| 型號： | ICS1892Y |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁數(shù)： | 67/148頁 |
| 文件大小： | 816K |
| 代理商： | ICS1892Y |
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Chapter 8
Management Register Set
ICS1892, Rev. D, 2/26/01
February 26, 2001
67
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
8.3.2
100Base-TX Full Duplex (bit 1.14)
The STA reads this bit to learn if the ICS1892 can support 100Base-TX, Full Duplex operations. The
ISO/IEC specification requires that the ICS1892
must set bit 1.14 to logic:
Zero if it cannot support 100Base-TX, full-duplex operations.
One if it can support 100Base-TX, full-duplex operations. (For the ICS1892, the default value of bit 1.14
is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the ICS1892
supports 100Base-TX, full-duplex operations.)
This bit 1.14 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in
Section 8.11, “Register 16:
Extended Control Register”
.]
8.3.3
100Base-TX Half Duplex (bit 1.13)
The STA reads this bit to learn if the ICS1892 can support 100Base-TX, half-duplex operations. The
ISO/IEC specification requires that the ICS1892 must set bit 1.13 to logic:
Zero if it cannot support 100Base-TX, half-duplex operations.
One if it can support 100Base-TX, half-duplex operations. (For the ICS1892, the default value of bit 1.13
is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the ICS1892
supports 100Base-TX, half-duplex operations.)
This bit 1.13 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in
Section 8.11, “Register 16:
Extended Control Register”
.]
8.3.4
10Base-T Full Duplex (bit 1.12)
The STA reads this bit to learn if the ICS1892 can support 10Base-T, full-duplex operations. The ISO/IEC
specification requires that the ICS1892 must set bit 1.12 to logic:
Zero if it cannot support 10Base-T, full-duplex operations.
One if it can support 10Base-T, full-duplex operations. (For the ICS1892, the default value of bit 1.12 is
logic one. Therefore, when an STA reads the Status Register, the STA is informed that the ICS1892
supports 10Base-T, full-duplex operations.)
This bit 1.12 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in
Section 8.11, “Register 16:
Extended Control Register”
.]
8.3.5
10Base-T Half Duplex (bit 1.11)
The STA reads this bit to learn if
the ICS1892 can support 10Base-T, half-duplex operations. The ISO/IEC
specification requires that the ICS1892 must set bit 1.11 to logic:
Zero if it cannot support 10Base-T, half-duplex operations.
One if it can support 10Base-T, half-duplex operations. (For the ICS1892, the default value of bit 1.11 is
logic one. Therefore, when an STA reads the Status Register, the STA is informed that the ICS1892
supports 10Base-T, half-duplex operations.)
Bit 1.11 of the ICS1892 Status Register is a Command Override Write bit., which allows an STA to alter the
default value of this bit. [See the description of bit 16.15, the Command Override Write Enable bit, in
Section 8.11, “Register 16: Extended Control Register”
.]
相關PDF資料 |
PDF描述 |
|---|---|
| ICS1892Y-10 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893Y-10 | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893 | 3.3-V 10Base-T/100Base-TX Integrated PHYceiver⑩ |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1892Y-10 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893_09 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver? |
| ICS1893AF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR) |
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