參數(shù)資料
型號： ICS1892Y
英文描述： 10Base-T/100Base-TX Integrated PHYceiver
文件頁數(shù)： 66/148頁
文件大?。?/td> 816K
代理商： ICS1892Y
ICS1892, Rev. D, 2/26/01
February 26, 2001
66
Chapter 8
Management Register Set
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
8.3
Register 1: Status Register
Table 8-6
lists the bits for the Status Register, an interface between the ICS1892 and the STA that has 16
bits of data. There are two types of status bits: some report the capabilities of the ICS1892, and some
indicate the state of signals used to monitor internal circuits.
The STA accesses the Status Register using the Serial Management Interface. During a reset, the
ICS1892 initializes the Status Register bits to pre-defined, default values.
Note:
For an explanation of acronyms used in
Table 8-5
, see
Chapter 1, “Abbreviations and Acronyms”
.
As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value
to all Reserved bits.
8.3.1
100Base-T4 (bit 1.15)
The STA reads this bit to learn if the ICS1892 can support 100Base-T4 operations. Bit 1.15 of the ICS1892
is permanently set to logic zero, which informs an STA that the ICS1892 cannot support 100Base-T4
operations.
Table 8-6.
Status Register (Register 1 [0x01])
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
cess
SF
De-
fault
Hex
1.15
100Base-T4
Always 0. (Not supported.)
N/A
RO
–
0
7
1.14
100Base-TX full duplex
Mode not supported
Mode supported
CW
–
1
1.13
100Base-TX half duplex
Mode not supported
Mode supported
CW
–
1
1.12
10Base-T full duplex
Mode not supported
Mode supported
CW
–
1
1.11
10Base-T half duplex
Mode not supported
Mode supported
CW
–
1
8
1.10
IEEE reserved
Always 0
N/A
CW
–
0
1.9
IEEE reserved
Always 0
N/A
CW
–
0
1.8
IEEE reserved
Always 0
N/A
CW
–
0
1.7
IEEE reserved
Always 0
N/A
CW
–
0
0
1.6
MF Preamble
suppression
PHY requires MF
Preambles
PHY does not require
MF Preambles
RO
–
0
1.5
Auto-Negotiation
complete
Auto-Negotiation is in
process, if enabled
Auto-Negotiation is
completed
RO
LH
0
1.4
Remote fault
No remote Fault Detected
Remote fault detected
RO
LH
0
1.3
Auto-Negotiation ability
N/A
Always 1: PHY has
Auto-Negotiation ability
RO
–
1
9
1.2
Link status
Link is invalid/down
Link is valid/established
RO
LL
0
1.1
Jabber detect
No jabber condition
Jabber condition
detected
RO
LH
0
1.0
Extended capability
N/A
Always 1: PHY has
extended capabilities
RO
–
1
相關PDF資料
PDF描述
ICS1892Y-10 10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-14 10Base-T/100Base-TX Integrated PHYceiver
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ICS1893Y-10 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
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相關代理商/技術參數(shù)
參數(shù)描述
ICS1892Y-10 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1892Y-14 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1893 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver
ICS1893_09 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver?
ICS1893AF 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR)
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