參數(shù)資料
型號： ICS1892Y-10
英文描述： 10Base-T/100Base-TX Integrated PHYceiver
文件頁數(shù)： 91/148頁
文件大?。?/td> 816K
代理商： ICS1892Y-10
Chapter 8
Management Register Set
ICS1892, Rev. D, 2/26/01
February 26, 2001
91
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
8.12.3
Auto-Negotiation Progress Monitor (bits 17.13:11)
The Auto-Negotiation Progress Monitor consists of the Auto-Negotiation Complete bit (bit 17.4) and the
three Auto-Negotiation Monitor bits (bits 17.13:11). The Auto-Negotiation Progress Monitor continually
examines the state of the Auto-Negotiation Process State Machine and reports the status of
Auto-Negotiation using the three Auto-Negotiation Monitor bits. Therefore, the value of these three bits
provides the status of the Auto-Negotiation Process.
These three bits are initialized to logic zero in one of the following ways:
A reset (see
Section 5.1, “Reset Operations”
)
Disabling Auto-Negotiation [see
Section 8.2.4, “Auto-Negotiation Enable (bit 0.12)”
]
Restarting Auto-Negotiation [see
Section 8.2.7, “Restart Auto-Negotiation (bit 0.9)”
]
If Auto-Negotiation is enabled, these bits continually latch the highest state that the Auto-Negotiation State
Machine achieves. That is, they are updated only if the binary value of the next state is greater than the
binary value of the present state as outlined in
Table 8-19
.
Note:
An MDIO read of these bits provides a history of the greatest progress achieved by the
auto-negotiation process. In addition, the MDIO read latches the present state of the
Auto-Negotiation State Machine for a subsequent read.
8.12.4
100Base
Receive Signal Lost (bit 17.10)
The 100Base Receive Signal Lost bit indicates to an STA whether the ICS1892 has lost its 100Base
Receive Signal. If this bit is set to a logic:
Zero, it indicates the Receive Signal has remained valid since the last read of this register.
One, it indicates the Receive Signal was lost after the last read of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see
Section
8.1.4.1, “Latching High Bits”
and
Section 8.1.4.2, “Latching Low Bits”
.)
Note:
This bit has no definition in 10Base-T mode.
Table 8-19.
Auto-Negotiation State Machine (Progress Monitor)
Auto-Negotiation State Machine
Auto-Negotiation Progress Monitor
Auto-
Negotiation
Complete Bit
(Bit 17.4)
Auto-
Negotiation
Monitor Bit 2
(Bit 17.13)
Auto-
Negotiation
Monitor Bit 1
(Bit 17.12)
Auto-
Negotiation
Monitor Bit 0
(Bit 17.11)
Idle
0
0
0
0
Parallel Detected
0
0
0
1
Parallel Detection Failure
0
0
1
0
Ability Matched
0
0
1
1
Acknowledge Match Failure
0
1
0
0
Acknowledge Matched
0
1
0
1
Consistency Match Failure
0
1
1
0
Consistency Matched
0
1
1
1
Auto-Negotiation Completed
Successfully
1
0
0
0
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參數(shù)描述
ICS1892Y-14 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1893 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver
ICS1893_09 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver?
ICS1893AF 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
ICS1893AFI 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
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