參數(shù)資料
型號： ICS1892Y-10
英文描述： 10Base-T/100Base-TX Integrated PHYceiver
文件頁數(shù)： 80/148頁
文件大?。?/td> 816K
代理商： ICS1892Y-10
ICS1892, Rev. D, 2/26/01
February 26, 2001
80
Chapter 8
Management Register Set
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
8.8
Register 6: Auto-Negotiation Expansion Register
Table 8-13
lists the bits for the Auto-Negotiation Expansion Register, which indicates the status of the
Auto-Negotiation process.
Note:
For an explanation of acronyms used in
Table 8-13
, see
Chapter 1, “Abbreviations and Acronyms”
.
As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value
to all Reserved bits.
8.8.1
IEEE Reserved Bits (bits 6.15:5)
The ISO/IEC specification reserves these bits for future use. When an STA:
Reads a reserved bit, the ICS1892 returns a logic zero.
Writes to a reserved bit, the STA must use the default value specified in this data sheet.
ICS uses some of these reserved bits to invoke auxiliary functions. To ensure proper operation of the
ICS1892, an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA
always write the default value of any reserved bits during all management register write operations.
Reserved bits 5.15:5 are Command Override Write (CW) bits. When the Command Register Override bit
(bit 16.15) is logic:
Zero, the ICS1892 isolates all STA writes to CW bits.
One, an STA can modify the value of these bits
Table 8-13.
Auto-Negotiation Expansion Register (register 6 [0x06])
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
cess
SF
De-
fault
Hex
6.15
IEEE reserved
Always 0
N/A
CW
–
0
0
6.14
IEEE reserved
Always 0
N/A
CW
–
0
6.13
IEEE reserved
Always 0
N/A
CW
–
0
6.12
IEEE reserved
Always 0
N/A
CW
–
0
6.11
IEEE reserved
Always 0
N/A
CW
–
0
0
6.10
IEEE reserved
Always 0
N/A
CW
–
0
6.9
IEEE reserved
Always 0
N/A
CW
–
0
6.8
IEEE reserved
Always 0
N/A
CW
–
0
6.7
IEEE reserved
Always 0
N/A
CW
–
0
0
6.6
IEEE reserved
Always 0
N/A
CW
–
0
6.5
IEEE reserved
Always 0
N/A
CW
–
0
6.4
Parallel detection fault
No Fault
Multiple technologies
detected
RO
LH
0
6.3
Link partner Next Page
able
Link partner is not Next
Page able
Link partner is Next Page
able
RO
–
0
4
6.2
Next Page able
Local device is not Next
Page able
Local device is Next Page
able
RO
–
1
6.1
Page received
Next Page not received
Next Page received
RO
LH
0
6.0
Link partner
Auto-Negotiation able
Link partner is not
Auto-Negotiation able
Link partner is
Auto-Negotiation able
RO
–
0
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ICS1893AFI 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR)
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