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參數(shù)資料
| 型號： | ICS1524M |
| 英文描述： | Dual Output Phase Controlled SSTL-3/PECL Clock Generator |
| 中文描述： | 雙輸出相控SSTL-3/PECL時(shí)鐘發(fā)生器 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 394K |
| 代理商： | ICS1524M |
15
ICS1524
ICS1524 Rev C 01/31/2003
.
Specific Layout Guidelines
1.
Digital Supply (VDD) –
Bypass pin 1 (VDD) to pin 2 (VSS) a 0.1-μF capacitor, located as close as possible to the pins. A
0.01-μF capacitor may be added for additional high frequency rejection.
2.
External Loop Filter –
Strongly recommended in All Designs.
Locate loop filter components as close to pins 8 and 9
(EXTFIL and EXTFILRET) as possible with minimum length traces
.
Typical loop filter values are 6.8K Ohms for the series
resistor, 3300 pF RF-type capacitor for the series capacitor, and 33 pF for the shunt capacitor. (For details, see the
Frequently
Asked Questions
part of the
ICS1523 Applications Guide
, FAQ2 and FAQ3.) A ground isolated, surface trace can be useful to
isolate this section from the rest of the board.
3.
Analog PLL Supply (VDDA) –
Decouple main VDD from pin 10 (VDDA) with a series ferrite bead. Bypass the supply end of
the bead with 4.7-μF. Bypass pin 10 to pin 11 (VSSA) with a 0.1-μF capacitor. A 0.01-μF capacitor may be added for additional
high frequency rejection. Locate these components as close as possible to the pins.
4.
PECL Current Set Resistor –
Locate PECL current-set resistor as close as possible to pin 24 (IREF). Bypass pin 24 to
ground with a 0.1 -μF capacitor.
5.
PECL Outputs –
Implement these outputs as microstrip transmission lines. The trace widths shown are for 75 Ohm charac-
teristic impedance. Locate any optional series “snubbing” resistors as close as possible to the source pins. If the termination
resistors are included on-board, locate them as close as possible to the load and connect directly to the power and ground
planes.
[These termination resistors are omitted if the load device implements them internally. For details, see the ICS application
note on microstrip and striplines (1572AN1) and within the
ICS1523 Applications Guide
, the application note on
Designing
a Custom Interface for the ICS1523
(1523AN4.)]
6.
Output Driver Supply –
Bypass pin 18 (VDDQ) to pin 19 (VSSQ) with a 0.1-μF capacitor, located as close as possible to the
pins. A 0.01-μF capacitor may be added for additional high frequency rejection.
7.
SSTL_3 Outputs –
SSTL_3 outputs can be used like conventional CMOS rail-to-rail logic or as a terminated transmission
line system at higher-output frequencies. With terminated outputs, the considerations of item 5, “PECL Outputs” apply. See
JEDEC documents JESD8-A and JESD8-8.
General Layout Guidelines
Use a PC board with at least four layers: one power, one ground, and two signal.
Use at least one 4.7 uF Tantalum (or similar) capacitor for global VDD bulk decoupling.
All supply voltages must be supplied from a common source and must ramp together.
Any flux or other board surface debris can degrade the performance of the external loop filter.
Ensure that the 1524 area of the board is free of contaminants.
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| ICS1524MT | 制造商:ICS 制造商全稱:ICS 功能描述:Dual Output Phase Controlled SSTL-3/PECL Clock Generator |
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