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參數(shù)資料
| 型號(hào)： | ICM7170IDG |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | XO, clock |
| 英文描述： | Microprocessor-Compatible, Real-Time Clock |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, CDIP24 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 77K |
| 代理商： | ICM7170IDG |
12-14
logical “0” CS as shown in Figures 2 and 3. The ICM7170
will also work satisfactorily with CS grounded. In this mode,
access to the ICM7170 is controlled by RD and WR only.
With the ALE (Address Latch Enable) input, the ICM7170
can be interfaced directly to microprocessors that use a
multiplexed address/data bus by connecting the address
lines A0 - A4 to the data lines D0 - D4. To address the chip,
the address is placed on the bus and ALE is strobed. On the
falling edge, the address and CS information is read into the
address latch and buffer. RD and WR are used in the same
way as on a non-multiplexed bus. If a non-multiplexed bus is
used, ALE should be connected to V
DD
.
Test Mode
The test mode is entered by setting D5 of the Command
Register to a logic “1”. This connects the 100Hz counter
directly to the oscillator’s output.
Oscillator Considerations
Load Design: A new oscillator load configuration, shown in
Figure 7, has been found that eliminates start-up problems
sometimes encountered with 32kHz tuning fork crystals.
Two conditions must be met for best oscillator performance:
the capacitive load must be matched to both the inverter and
crystal to provide the ideal conditions for oscillation, and the
resonant frequency of the oscillator must be adjustable to
the desired frequency. In the original design (Figure 8),
these two goals were often at odds with each other; either
the oscillator was trimmed to frequency by detuning the load
circuit, or stability was increased at the expense of absolute
frequency accuracy.
The new load configuration (Figure 6) allows these two
conditions to be met independently. The two load capacitors,
C1 and C2, provide a fixed load to the oscillator and crystal.
C3 adjusts the frequency that the circuit resonates at by
reducing the effective value of the crystal's motional
capacitance, C0. This minute adjustment does not
appreciably change the load of the overall system, therefore,
stability is no longer affected by tuning. Typical values for
these capacitors are shown in Table 5. C1 and C2 must
always be greater than twice the crystal’s recommended load
capacitance in order for C3 to be able to trim the frequency.
Some experimentation may be necessary to determine the
ideal values of C1 and C2 for a particular crystal.
+
-
POSITIVE SUPPLY RAIL
(+5V)
PIN 23
PIN 14
BATTERY
R2
2K
PIN 13
DIGITAL GROUND
V
DD
V
SS
V
BACK
V
DD
V
IG
CMOS COMPARATOR
V
TH
1.0V
V
IG
INTERNAL GROUND
I/O DISABLE
V
DD
FIGURE 6. SIMPLIFIED ICM7170 BATTERY BACKUP CIRCUIT
OSC IN
10
ICM7170
OSC OUT
V
DD
23
C1
C2
C3
X1
9
V
DD
FIGURE 7. NEW OSCILLATOR CONFIGURATION
OSC IN
10
ICM7170
OSC OUT
V
DD
23
C1
C2
X1
9
V
DD
C1
≈
2 x LOAD
C2
≈
5pF - 35pF
FIGURE 8. ORIGINAL OSCILLATOR CONFIGURATION
ICM7170
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