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參數(shù)資料
| 型號： | ICL7112LCDL |
| 廠商： | INTERSIL CORP |
| 元件分類： | ADC |
| 英文描述： | 2.0 Gbps 4x4 Crosspoint Switch 38-TSSOP -40 to 85 |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP40 |
| 封裝： | CERDIP-40 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 758K |
| 代理商： | ICL7112LCDL |
6-9
Memory Access (DMA) controller as shown in Figure 8.
Applications
Figure 9 shows a typical application of the ICL7112 12- bit
A/D converter. A bipolar input voltage range of +10V to -10V
is the result of using the current through R
2
to force a 1/2
scale offset on the input amplifier (A
1
). The output of A
1
swings from 0V to -1 0V. The overall gain of the A/D is varied
by adjusting the 100
trim resistor, R
5
. Since the ICL7112 is
automatically zeroed every conversion, the system gain and
offset stability will be superb as long as a reference with a
tempco of 1ppm/
o
C and stable external resistors are used.
If is important to note that since the 7112’s DAC current
flows in A
1
, the amplifier should be a wideband (GBW >
20MHz) type to minimize errors.
The clock for the ICL7112 is taken from whatever system
clock is available and divided down to the level for a conver-
sion time of 40
μ
s. Output data is controlled by the BUS and
A
0
inputs. Here they are set for 8-bit bus operation with BUS
grounded and A
0
under the control of the address decode
section of the external system.
Because the ICL7112’s internal accumulator generates
accurate output data for input signals as much as 3% greater
than full-scale, and because the converter’s OVR output
flags overrange inputs, a simple microprocessor routine can
be employed to precisely measure and correct for system
gain and offset errors. Figure 10 shows a typical data acqui-
sition system that uses a 10V reference, input signal multi-
plexer, and input signal Track/Hold amplifier. Two of the
multiplexer’s input channels are dedicated to sampling the
system analog ground and reference voltage. Here, as in
Figure 9, bipolar operation is accommodated by an offset
resistor between the reference voltage and the summing
junction of A
1
. A flip-flop in IC
3
sets 1
C2
’s Track/Hold input
after the microprocessor has initiated a WR command, and
resets when EOC goes high at the end of the conversion.
The first step in the system calibration routine is to select the
multiplexer channel that is connected to system analog
ground and initiate a conversion cycle for the ICL7112. The
results represent the system offset error which comes from
the sum of the offsets from IC
1
, IC
2
, and A
1
. Next the chan-
nel connected to the reference voltage is selected and mea-
sured. These results, minus the system offset error,
represent the system full-scale range. A gain error correction
factor can be derived from this data. Since the lCL7112 pro-
vides valid data for inputs that exceed full-scale by as much
as 3%, the OVR output can be thought of as a valid 13th
data bit. Whenever the OVR bit is high, however, the total
12-bit result should be checked to ensure that it falls within
100% and 103% of full-scale. Data beyond 103% of full-
scale should be discarded.
Clock Considerations
The ICL7112 provides an internal inverter which is brought
out to pins OSC1 and OSC2, for crystal or ceramic resonator
oscillator operation. The clock frequency is calculated from:
f
CLK
=
CONV
-----------------
ICL7112
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PDF描述 |
|---|---|
| ICL7112LMDL | 2.0 Gbps 4x4 Crosspoint Switch 38-TSSOP -40 to 85 |
| ICL7112 | Dual LVDS Receiver 8-SOIC -40 to 85 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICL7112LIDL | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, High-Speed, CMOS uP-Compatible A/D Converter |
| ICL7112LMDL | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, High-Speed, CMOS uP-Compatible A/D Converter |
| ICL7115 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:N-CHANNEL JFET |
| ICL7115JCDL | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:14-Bit High-Speed CMOS UP-Compatible A/D Converter |
| ICL7115JCJL | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Data Acquisition |
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