參數(shù)資料
型號(hào): IBMN364804CT3C-360
英文描述: x8 SDRAM
中文描述: x8 SDRAM內(nèi)存
文件頁數(shù): 26/71頁
文件大?。?/td> 1251K
代理商: IBMN364804CT3C-360
IBMN364164
IBMN364404
64Mb Synchronous DRAM - Die Revision C
IBMN364804
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 26 of 71
19L3265.E35856B
1/01
Burst write operations will be terminated by the Precharge command. The last write data that will be properly
stored in the device is that write data that is presented to the device a number of clock cycles prior to the Pre-
charge command equal to the Data-in to Precharge delay, t
DPL
.
Precharge Termination of a Burst Write
COMMAND
NOP
NOP
NOP
WRITE Ax
0
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
DIN Ax
1
DIN Ax
2
t
DPL
DIN Ax
0
t
CK2,
DQs
CAS latency = 2
NOP
DIN Ax
1
DIN Ax
2
DIN Ax
0
t
CK3,
DQs
CAS latency = 3
DQM
Precharge A
t
DPL
is an asynchronous timing and may be completed in one or two clock cycles
depending on clock cycle time.
(Burst Length = 8, CAS Latency = 2, 3)
t
DPL
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