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參數(shù)資料
| 型號(hào)： | HYS72T512122HFN-3.7-A |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM |
| 中文描述： | 512M X 72 DDR DRAM MODULE, PDMA240 |
| 封裝： | GREEN, DIMM-240 |
| 文件頁數(shù)： | 4/32頁 |
| 文件大小： | 880K |
| 代理商： | HYS72T512122HFN-3.7-A |
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Internet Data Sheet
Rev. 1.1, 2006-11
03292006-WK9O-3A6G
4
HYS72T512[0/1]22HFN–3.7–A
1.2
Description
This document describes the electrical and mechanical
features of Qimonda’s 240-pin, PC2-4200F ECC type, Fully
Buffered Double-Data-Rate Two Synchronous DRAM Dual
In-Line Memory Modules (DDR2 SDRAM FB-DIMMs). Fully
Buffered DIMMs use commodity DRAMs isolated from the
memory channel behind a buffer on the DIMM. They are
intended for use as main memory when installed in systems
such as servers and workstations. PC2-4200 refers to the
DIMM naming convention indicating the DDR2 SDRAMs
running at 266 MHz clock speed and offering 4200 MB/s peak
bandwidth. FB-DIMM features a novel architecture including
the Advanced Memory Buffer. This single chip component,
located in the center of each DIMM, acts as a repeater and
buffer for all signals and commands which are exchanged
between the host controller and the DDR2 SDRAMs including
data in- and output. The AMB communicates with the host
controller and / or the adjacent DIMMs on a system board
using an Industry Standard High-Speed Differential Point-to-
Point Link Interface at 1.5 V.
The Advanced Memory Buffer also allows buffering of
memory traffic to support large memory capacities. All
memory control for the DRAM resides in the host, including
memory request initiation, timing, refresh, scrubbing, sparing,
configuration access, and power management. The
Advanced Memory Buffer interface is responsible for handling
channel and memory requests to and from the local DIMM
and for forwarding requests to other DIMMs on the memory
channel. Fully Buffered DIMM provides a high memory
bandwidth, large capacity channel solution that has a narrow
host interface. The maximum memory capacity is 288 DDR2
SDRAM devices per channel or 8 DIMMs.
TABLE 2
Ordering Information (Pb-free components and assembly)
TABLE 3
Address Format
Product Type
1)
1) All product types end with a place code, designating the silicon die revision. Example: HYS 72T64000HFA-3.7-A, indicating Rev. A dice
are used for DDR2 SDRAM components. To learn more on QIMONDA DDR2 module and component nomenclature see section 8 of this
datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, e.g. “PC2-4200F-444-11-A”, where 4200F means
Fully Buffered DIMM with 4.26 GB/sec. Module Bandwidth and “444-11” means CAS latency = 4, t
rcd
latency = 4 and t
rp
latency = 4 using
JEDEC SPD Revision 1.1 and assembled on Raw Card “A”.
Compliance Code
2)
Description
SDRAM Technology
PC2-4200F (DDR2-533):
HYS72T512022HFN–3.7–A
HYS72T512122HFN–3.7–A
4GB 2R
×
4 PC2-4200F–444–11–D
4GB 2R
×
4 PC2-4200F–444–11–D
2 Ranks, FB–DIMM
2 Ranks, FB–DIMM
2Gbit (
×
4)
2Gbit (
×
4)
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of
SDRAMs
# of row/bank/columns bits
Raw
Card
4 GB
512M
×
72
2
ECC
18
13/2/11
D
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72T512341HKP-3.7-B | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T512341HKP-5-B | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T512341HHP | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T512341HHP-3.7-B | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T512341HHP-5-B | 240-Pin Registered DDR2 SDRAM Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T512341HHP | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T512341HHP-3.7-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T512341HHP-5-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T512341HJP | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T512341HJP-3.7-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
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