參數(shù)資料
型號: HYS72T512122HFN-3.7-A
廠商: QIMONDA AG
元件分類: DRAM
英文描述: 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM
中文描述: 512M X 72 DDR DRAM MODULE, PDMA240
封裝: GREEN, DIMM-240
文件頁數(shù): 23/32頁
文件大?。?/td> 880K
代理商: HYS72T512122HFN-3.7-A
Internet Data Sheet
Rev. 1.1, 2006-11
03292006-WK9O-3A6G
23
HYS72T512[0/1]22HFN–3.7–A
6
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
Table 15 “PC2–4200F–444” on Page 23
TABLE 15
PC2–4200F–444
Product Type
HYS72T512022HFN–3.7–A HYS72T512122HFN–3.7–A
Organization
4 GByte
4 GByte
×
72
×
72
2 Ranks (
×
4)
2 Ranks (
×
4)
Label Code
PC2–4200F–444
PC2–4200F–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SPD Size CRC / Total / Used
SPD Revision
Key Byte / DRAM Device Type
Voltage Level of this Assembly
SDRAM Addressing
Module Physical Attributes
Module Type
Module Organization
Fine Timebase (FTB) Dividend and Divisor
Medium Timebase (MTB) Dividend
Medium Timebase (MTB) Divisor
t
CK.MIN
(min. SDRAM Cycle Time)
t
CK.MAX
(max. SDRAM Cycle Time)
CAS Latencies Supported
t
CAS.MIN
(min. CAS Latency Time)
Write Recovery Values Supported (WR)
t
WR.MIN
(Write Recovery Time)
Write Latency Times Supported
Additive Latency Times Supported
t
RCD.MIN
(min. RAS# to CAS# Delay)
t
RRD.MIN
(min. Row Active to Row Active Delay)
t
RP.MIN
(min. Row Precharge Time)
92
11
09
12
49
23
07
10
00
01
04
0F
20
33
3C
32
3C
72
50
3C
1E
3C
92
11
09
12
49
23
07
10
00
01
04
0F
20
33
3C
32
3C
72
50
3C
1E
3C
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