參數(shù)資料
型號(hào)： HYS72T512022EP
廠商： QIMONDA
英文描述： 240-Pin Dual Die Registered DDR2 SDRAM Modules
中文描述： 240針雙模具注冊(cè)DDR2 SDRAM內(nèi)存模塊
文件頁(yè)數(shù)： 22/36頁(yè)
文件大?。?/td> 980K
代理商： HYS72T512022EP
Internet Data Sheet
Rev. 1.0, 2007-03
03292007-RHOW-C5L6
22
HYS72T[512/1G]0x2EP–[3S/3.7]–B
Registerd DDR2 SDRAM Module
Data hold skew factor
Average periodic refresh Interval
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
Active bank A to Active bank B command
period
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-
Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read
command (slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
Write recovery time for write with Auto-
Precharge
1) For details and notes see the relevant Qimonda component data sheet
2)
V
DDQ
= 1.8 V
±
0.1 V;
V
DD
= 1.8 V
±
0.1 V.
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
7) The output timing reference voltage level is
V
TT
.
8) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
t
QHS
t
REFI
t
REFI
t
RFC
—
—
—
127.5
400
7.8
3.9
—
ps
μ
s
μ
s
ns
—
14)15)
16)18)
17)
t
RP
t
RP
t
RPRE
t
RPST
t
RRD
t
RP
+ 1
t
CK
15 + 1
t
CK
0.9
0.40
7.5
—
—
1.1
0.60
—
ns
ns
t
CK
t
CK
ns
—
—
14)
14)
14)18)
t
RRD
10
—
ns
16)22)
t
RTP
t
WPRE
t
WPST
t
WR
7.5
0.25
0.40
15
—
—
0.60
—
ns
t
CK
t
CK
ns
—
—
19)
—
t
WTR
t
XARD
7.5
2
—
—
ns
t
CK
20)
21)
t
XARDS
6 – AL
—
t
CK
21)
t
XP
2
—
t
CK
—
t
XSNR
t
XSRD
WR
t
RFC
+10
200
t
WR
/
t
CK
—
—
—
ns
t
CK
t
CK
—
—
22)
Parameter
Symbol
DDR2–533
Unit
Note
1)2)3)4)5)
6)7)
Min.
Max.
相關(guān)PDF資料
PDF描述
HYS72T512022EP-3.7-B 240-Pin Dual Die Registered DDR2 SDRAM Modules
HYS72T512022EP-3S-B 240-Pin Dual Die Registered DDR2 SDRAM Modules
HYS72T512022ER 240-Pin Dual Die Registered DDR2 SDRAM Modules
HYS72T512022HFN-3.7-A 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM
HYS72T512122HFN-3.7-A 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T512022EP-3.7-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Dual Die Registered DDR2 SDRAM Modules
HYS72T512022EP-3S-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Dual Die Registered DDR2 SDRAM Modules
HYS72T512022ER 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Dual Die Registered DDR2 SDRAM Modules
HYS72T512022HFN-3.7-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM
HYS72T512022HR 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
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