- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385437 > HYS72T32000HU-3S-A (QIMONDA AG) 240-Pin Unbuffered DDR2 SDRAM Modules PDF資料下載
參數(shù)資料
| 型號： | HYS72T32000HU-3S-A |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 240-Pin Unbuffered DDR2 SDRAM Modules |
| 中文描述： | 32M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封裝： | GREEN, DIMM-240 |
| 文件頁數(shù)： | 34/73頁 |
| 文件大?。?/td> | 1574K |
| 代理商： | HYS72T32000HU-3S-A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁
Internet Data Sheet
Rev. 1.41, 2006-11
03062006-0GN5-WTPW
34
HYS[64/72]T[16/32/64]0xxHU–[2.5/../5]–A
Unbuffered DDR2 SDRAM Modules
3.4
I
DD
Specifications and Conditions
List of tables defining
I
DD
Specifications and Conditions.
Table 22 “IDD Measurement Conditions” on Page 34
Table 23 “Definitions for IDD” on Page 35
Table 24 “I DD Specification for HYS[64/72]T[32/64]xxxHU-[2.5/2.5F]–A” on Page 36
Table 25 “I DD Specification for HYS[64/72]T[32/64]xxxHU-[3/3S]–A” on Page 37
Table 26 “I DD Specification for HYS[64/72]T[16/32/64]xxxHU-[3.7/5]–A” on Page 38
TABLE 22
I
DD
Measurement Conditions
Parameter
Symbol Note
1)2)3)4)5)
Operating Current 0
One bank Active - Precharge;
t
CK
=
t
CK.MIN
,
t
RC
=
t
RC.MIN
,
t
RAS
=
t
RAS.MIN
, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge;
I
OUT
= 0 mA, BL = 4,
t
CK
=
t
CK.MIN
,
t
RC
=
t
RC.MIN
,
t
RAS
=
t
RAS.MIN
,
t
RCD
=
t
RCD.MIN
, AL = 0, CL = CL
MIN
; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK
=
t
CK.MIN
; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK
=
t
CK.MIN
; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
MIN
;
t
CK
=
t
CK.MIN
;
t
RAS
=
t
RAS.MAX
,
t
RP
=
t
RP.MIN
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
I
OUT
= 0 mA.
Active Power-Down Current
All banks open;
t
CK
=
t
CK.MIN
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
All banks open;
t
CK
=
t
CK.MIN
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current - Burst Read
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
MIN
;
t
CK
=
t
CKMIN
;
t
RAS
=
t
RASMAX
;
t
RP
=
t
RPMIN
; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING;
I
OUT
= 0mA.
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
MIN
;
t
CK
=
t
CK.MIN
;
t
RAS
=
t
RAS.MAX.
,
t
RP
=
t
RP.MAX
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
t
CK
=
t
CK.MIN
., Refresh command every
t
RFC
=
t
RFC.MIN
interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
I
DD0
I
DD1
6)
I
DD2N
I
DD2P
I
DD2Q
I
DD3N
I
DD3P(0)
I
DD3P(1)
I
DD4R
6)
I
DD4W
I
DD5B
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72T32000HU-5-A | 240-Pin Unbuffered DDR2 SDRAM Modules |
| HYS72T64020HU | 240-Pin Unbuffered DDR2 SDRAM Modules |
| HYS72T64020HU-2.5-A | 240-Pin Unbuffered DDR2 SDRAM Modules |
| HYS72T64020HU-25F-A | 240-Pin Unbuffered DDR2 SDRAM Modules |
| HYS72T64020HU-3-A | 240-Pin Unbuffered DDR2 SDRAM Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T32000HU-5-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules |
| HYS72T512020HR | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered-DDR2-SDRAM Modules |
| HYS72T512020HR-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered-DDR2-SDRAM Modules |
| HYS72T512020HR-5-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered-DDR2-SDRAM Modules |
| HYS72T512022EP | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Dual Die Registered DDR2 SDRAM Modules |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。