參數(shù)資料
型號(hào): HYS72T256020HU-3.7-A
廠商: QIMONDA AG
元件分類(lèi): DRAM
英文描述: 240-Pin Unbuffered DDR2 SDRAM Modules
中文描述: 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝: GREEN, DIMM-240
文件頁(yè)數(shù): 21/61頁(yè)
文件大?。?/td> 1365K
代理商: HYS72T256020HU-3.7-A
Internet Data Sheet
Rev. 1.32, 2006-09
03062006-5RK8-1X8J
21
HYS[64/72]T256xxxHU–[3/…/5]–A
Unbuffered DDR2 SDRAM Modules
3.3.2
AC Timing Parameters
List of AC timing parameter tables.
Table 17 “Timing Parameter by Speed Grade - DDR2–667” on Page 21
Table 18 “Timing Parameter by Speed Grade - DDR2–533” on Page 26
Table 19 “Timing Parameter by Speed Grade - DDR2-400” on Page 29
TABLE 17
Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Unit
Note
1)2)3)4)5)6)7)
8)
Min.
Max.
DQ output access time from CK / CK
DQS output access time from CK / CK
Average clock high pulse width
Average clock low pulse width
Average clock period
DQ and DM input setup time
DQ and DM input hold time
Control & address input pulse width for each input
t
IPW
DQ and DM input pulse width for each input
Data-out high-impedance time from CK / CK
DQS/DQS low-impedance time from CK / CK
DQ low impedance time from CK/CK
DQS-DQ skew for DQS & associated DQ signals
t
DQSQ
CK half pulse width
t
AC
t
DQSCK
t
CH.AVG
t
CL.AVG
t
CK.AVG
t
DS.BASE
t
DH.BASE
–450
–400
0.48
0.48
3000
100
175
0.6
0.35
t
AC.MIN
2 x
t
AC.MIN
Min(
t
CH.ABS
,
t
CL.ABS
)
t
HP
t
QHS
RL–1
– 0.25
+450
+400
0.52
0.52
8000
––
––
t
AC.MAX
t
AC.MAX
t
AC.MAX
240
__
ps
ps
t
CK.AVG
t
CK.AVG
ps
ps
ps
t
CK.AVG
t
CK.AVG
ps
ps
ps
ps
ps
9)
9)
10)11)
10)11)
12)13)14)
13)14)15)
t
DIPW
t
HZ
t
LZ.DQS
t
LZ.DQ
9)16)
9)16)
9)16)
17)
t
HP
18)
DQ hold skew factor
DQ/DQS output hold time from DQS
Write command to DQS associated clock edges
DQS latching rising transition to associated clock
edges
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write postamble
Write preamble
Address and control input setup time
Address and control input hold time
Read preamble
Read postamble
Active to precharge command
t
QHS
t
QH
WL
t
DQSS
340
ps
ps
nCK
t
CK.AVG
19)
20)
+ 0.25
21)
t
DQSH
t
DQSL
t
DSS
t
DSH
t
WPST
t
WPRE
t
LS.BASE
t
LH.BASE
t
RPRE
t
RPST
t
RAS
0.35
0.35
0.2
0.2
0.4
0.35
200
275
0.9
0.4
45
0.6
1.1
0.6
70000
t
CK.AVG
t
CK.AVG
t
CK.AVG
t
CK.AVG
t
CK.AVG
t
CK.AVG
ps
ps
t
CK.AVG
t
CK.AVG
ns
21)
21)
22)23)
23)24)
25)26)
25)27)
28)
相關(guān)PDF資料
PDF描述
HYS72T256020HU-3-A 240-Pin Unbuffered DDR2 SDRAM Modules
HYS72T256020HU-5-A 240-Pin Unbuffered DDR2 SDRAM Modules
HYS72T256023 240-Pin Registered DDR2 SDRAM Modules
HYS72T256023HR 240-Pin Registered DDR2 SDRAM Modules
HYS72T256023HR-5-A 240-Pin Registered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T256020HU-3-A 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules
HYS72T256020HU-3S-A 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules
HYS72T256020HU-5-A 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules
HYS72T256023 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256023HR 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules