參數(shù)資料
型號： HYS72T256000ER
廠商： QIMONDA
英文描述： 240-Pin Registered DDR2 SDRAM Modules
中文描述： 240針DDR2 SDRAM的注冊模塊
文件頁數(shù)： 15/33頁
文件大?。?/td> 892K
代理商： HYS72T256000ER
Internet Data Sheet
Rev. 1.0, 2006-10
10202006-EHWJ-OT02
15
HYS72T256000ER-[3.7/5]-B
Registerd DDR2 SDRAM Module
3.3
Timing Characteristics
This chapter describes the timing characteristics.
3.3.1
Speed Grade Definitions
All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications(
t
CK
= 5ns with
t
RAS
= 40ns).
Speed Grade Definitions:
Table 12
for DDR2–533C and
Table 13
for DDR2–400B
TABLE 12
Speed Grade Definition Speed Bins for DDR2–533C
TABLE 13
Speed Grade Definition Speed Bins for DDR2-400B
Speed Grade
DDR2–533C
Unit
Note
QAG Sort Name
–3.7
CAS-RCD-RP latencies
4–4–4
t
CK
Parameter
Symbol
Min.
Max.
—
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
t
CK
t
CK
t
CK
t
RAS
t
RC
t
RCD
t
RP
5
3.75
3.75
45
60
15
15
8
8
8
70000
—
—
—
ns
ns
ns
ns
ns
ns
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
4) The output timing reference voltage level is
V
TT
.
5)
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
t
REFI
.
1)2)3)4)
1)2)3)4)
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Speed Grade
DDR2–400B
Unit
Note
QAG Sort Name
–5
CAS-RCD-RP latencies
3–3–3
t
CK
Parameter
Symbol
Min.
Max.
—
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
t
CK
t
CK
t
CK
t
RAS
5
5
5
40
8
8
8
70000
ns
ns
ns
ns
1)2)3)4)
1)2)3)4)
1)2)3)4)
Row Active Time
1)2)3)4)5)
相關(guān)PDF資料
PDF描述
HYS72T256000ER-3.7-B 240-Pin Registered DDR2 SDRAM Modules
HYS72T256000ER-5-B 240-Pin Registered DDR2 SDRAM Modules
HYS72T256020EU-2.5-B 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T256020EU-25F-B 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T256020EU-3.7-B 240-Pin unbuffered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T256000ER-3.7-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256000ER-5-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256000HR 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules
HYS72T256000HR-3.7-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules
HYS72T256000HR-3S-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules
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