參數(shù)資料
型號(hào)： HYS72T1G242EP-3.7-C
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 240-Pin Dual Die Registered DDR2 SDRAM Modules
中文描述： 1G X 72 DDR DRAM MODULE, 0.7 ns, DMA240
封裝： GREEN, RDIMM-240
文件頁(yè)數(shù)： 29/43頁(yè)
文件大?。?/td> 1309K
代理商： HYS72T1G242EP-3.7-C
Internet Data Sheet
Rev. 1.0, 2007-07
07242007-LR08-OZC0
29
HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
3.3.3
ODT AC Electrical Characteristics
This chapter describes the ODT AC electrical characteristics.
TABLE 18
ODT AC Characteristics and Operating Conditions for all bins DDR2-667 & DDR2-800
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
t
AOND
t
AON
t
AONPD
t
AOFD
t
AOF
t
AOFPD
t
ANPD
t
AXPD
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
2
t
AC.MIN
t
AC.MIN
+ 2 ns
2.5
t
AC.MIN
t
AC.MIN
+ 2 ns
3
8
2
t
AC.MAX
+ 0.7 ns
2
t
CK +
t
AC.MAX
+ 1 ns
2.5
t
AC.MAX
+ 0.6 ns
2.5
t
CK +
t
AC.MAX
+ 1 ns
—
—
n
CK
ns
ns
n
CK
ns
ns
n
CK
n
CK
1)
1) New units, “t
” and “
n
”, are introduced in DDR2-667 and DDR2-800. Unit “
t
” represents the actual
t
of the input clock
under operation. Unit “
n
CK
” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, “
t
CK
” is used for both concepts. Example:
t
XP
= 2 [
n
CK
] means; if Power Down exit is registered at
T
m
, an Active command may
be registered at
T
m
+ 2, even if (
T
m
+ 2 -
T
m
) is 2 x
t
CK.AVG
+
t
ERR.2PER(Min)
.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the
ODT resistance is fully on. Both are measured from
t
, which is interpreted differently per speed bin. For DDR2-667/800,
t
AOND
is 2 clock
cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from
t
AOFD
, which is interpreted differently per speed bin. For DDR2-667/800, iIf
t
CK(avg)
= 3 ns is assumed,
t
AOFD
is 1.5
ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the
actual input clock edges.
1)2)
1)
1)
1)3)
1)
1)
1)
相關(guān)PDF資料
PDF描述
HYS72T1G242EP-3-C 240-Pin Dual Die Registered DDR2 SDRAM Modules
HYS72T1G242EP-3S-C 240-Pin Dual Die Registered DDR2 SDRAM Modules
HYS72T256000ER 240-Pin Registered DDR2 SDRAM Modules
HYS72T256000ER-3.7-B 240-Pin Registered DDR2 SDRAM Modules
HYS72T256000ER-5-B 240-Pin Registered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T1G242EP-3-C 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Dual Die Registered DDR2 SDRAM Modules
HYS72T1G242EP-3S-C 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Dual Die Registered DDR2 SDRAM Modules
HYS72T256000ER 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256000ER-3.7-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256000ER-5-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
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