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參數(shù)資料
| 型號(hào)： | HYS72T128000EU-2.5-C2 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.4 ns, DMA240 |
| 封裝： | GREEN, UDIMM-240 |
| 文件頁數(shù)： | 57/59頁 |
| 文件大小： | 3071K |
| 代理商： | HYS72T128000EU-2.5-C2 |
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HYS[64/72]T[128/256]0x0EU–[19F/1.9/25F/2.5/3S]–C2
Unbuffered DDR2 SDRAM Modules
Internet Data Sheet
Rev. 1.00, 2008-06
7
12032007-I9KE-FFWO
73
WE
I
SSTL
Write Enable
Address Signals
71
BA0
I
SSTL
Bank Address Bus 1:0
Selects which DDR2 SDRAM internal bank of four or eight is activated.
190
BA1
I
SSTL
54
BA2
I
SSTL
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
—
Not Connected
Less than 1Gb DDR2 SDRAMS
188
A0
I
SSTL
Address Bus 12:0
During a Bank Activate command cycle, defines the row address when
sampled at the crosspoint of the rising edge of CK and falling edge of CK.
During a Read or Write command cycle, defines the column address when
sampled at the cross point of the rising edge of CK and falling edge of CK. In
addition to the column address, AP is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If AP is HIGH, autoprecharge is
selected and BA0-BAn defines the bank to be precharged. If AP is LOW,
autoprecharge is disabled. During a Precharge command cycle, AP is used
in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is
HIGH, all banks will be precharged regardless of the state of BA0-BAn inputs.
If AP is LOW, then BA0-BAn are used to define which bank to precharge.
183
A1
I
SSTL
63
A2
I
SSTL
182
A3
I
SSTL
61
A4
I
SSTL
60
A5
I
SSTL
180
A6
I
SSTL
58
A7
I
SSTL
179
A8
I
SSTL
177
A9
I
SSTL
70
A10
I
SSTL
AP
I
SSTL
57
A11
I
SSTL
176
A12
I
SSTL
196
A13
I
SSTL
Address Signal 13
Note: 1 Gbit based module and 512M
×4/×8
NC
—
Not Connected
Note: Module based on 1 Gbit
×16Module based on 512 Mbit ×16 or smaller
174
A14
I
SSTL
Address Signal 14
Note: Modules based on 2 Gbit
NC
—
Not Connected
Note: Modules based on 1 Gbit or smaller
Data Signals
3
DQ0
I/O
SSTL
Data Bus 63:0
Data Input / Output pins
4
DQ1
I/O
SSTL
9
DQ2
I/O
SSTL
10
DQ3
I/O
SSTL
122
DQ4
I/O
SSTL
123
DQ5
I/O
SSTL
128
DQ6
I/O
SSTL
129
DQ7
I/O
SSTL
Ball No.
Name
Pin
Type
Buffer
Type
Function
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72T64000EP-3.7-B2 | 64M X 72 DDR DRAM MODULE, DMA240 |
| HZ20-1 | 19.25 V, 0.5 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE, DO-35 |
| HZ6B1L | 5.65 V, 0.4 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE, DO-35 |
| HZ9.1CP | 9.65 V, 1 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE, DO-41 |
| HZB6.8MWA | 6.8 V, 0.2 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T128000GR | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDR2 Registered Memory Modules |
| HYS72T128000GR-37-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDR2 Registered Memory Modules |
| HYS72T128000GR-5-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDR2 Registered Memory Modules |
| HYS72T128000HP | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T128000HP-2.5-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
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