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參數(shù)資料
| 型號： | HYS72D64320HBR-5-C |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 184-Pin Registered Double Data Rate SDRAM Module |
| 中文描述： | 64M X 72 DDR DRAM MODULE, 0.5 ns, DMA184 |
| 封裝： | GREEN, DIMM-184 |
| 文件頁數(shù)： | 13/50頁 |
| 文件大?。?/td> | 1158K |
| 代理商： | HYS72D64320HBR-5-C |
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Internet Data Sheet
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
13
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
3.2
Current Conditions
This chapter describes the Conditions.
TABLE 10
I
DD
Conditions
Parameter
Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE
≤
V
IL,MAX
Precharge Floating Standby Current
CS
≥
V
IH,,MIN
, all banks idle; CKE
≥
V
IH,MIN
;
address and other control inputs changing once per clock cycle;
V
IN
=
V
REF
for DQ, DQS and DM.
Precharge Quiet Standby Current
CS
≥
V
IHMIN
, all banks idle; CKE
≥
V
IH,MIN
;
V
IN
=
V
REF
for DQ, DQS and DM;
address and other control inputs stable at
≥
V
IH,MIN
or
≤
V
IL,MAX
.
Active Power-Down Standby Current
one bank active; power-down mode; CKE
≤
V
ILMAX
;
V
IN
=
V
REF
for DQ, DQS and DM.
Active Standby Current
one bank active; CS
≥
V
IH,MIN
; CKE
≥
V
IH,MIN
;
t
RC
=
t
RAS,MAX
;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50 % of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B;
I
OUT
= 0 mA
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50 % of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
t
RC
=
t
RFCMIN
, burst refresh
Self-Refresh Current
CKE
≤
0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
I
DD0
I
DD1
I
DD2P
I
DD2F
I
DD2Q
I
DD3P
I
DD3N
I
DD4R
I
DD4W
I
DD5
I
DD6
I
DD7
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| HYS72D64320HBR-6-C | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64300HU-5-C | 184-Pin Unbuffered Double Data Rate SDRAM |
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| HYS72D64301HBR_07 | 184-Pin Registered Double-Data-Rate SDRAM Module |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72D64320HBR-6-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64320HU-5-C | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules |
| HYS72D64320HU-6-C | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules |
| HYS72D64500GR-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HYS72D64500GR-7-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?512MB (64Mx72) PC2100 1-bank? |
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