參數(shù)資料
型號: HYS72D64300HBR-7-C
廠商: QIMONDA AG
元件分類: DRAM
英文描述: 184-Pin Registered Double Data Rate SDRAM Module
中文描述: 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184
封裝: GREEN, DIMM-184
文件頁數(shù): 6/50頁
文件大?。?/td> 1158K
代理商: HYS72D64300HBR-7-C
Internet Data Sheet
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
6
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
2
Pin Configuration
The pin configuration of the Registered DDR SDRAM DIMM
is listed by function in
Table 4
(184 pins). The abbreviations
used in columns Pin and Buffer Type are explained in
Table 5
and
Table 6
respectively. The pin numbering is depicted in
Figure 1
.
TABLE 4
Pin Configuration of RDIMM
Pin
#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
137
CK0
138
CK0
21
CKE0
111
CKE1
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Clock Signal
Complement Clock
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-rank module
Note:
1
-rank module
NC
NC
SSTL
Control Signals
157
S0
158
S1
I
I
SSTL
SSTL
Chip Select of Rank 0
Chip Select of Rank 1
Note: 2-ranks module
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
Register Reset
NC
RAS
CAS
WE
RESET
NC
I
I
I
I
SSTL
SSTL
SSTL
LV-
CMOS
154
65
63
10
Address Signals
59
BA0
52
BA1
48
A0
43
A1
41
A2
130
A3
37
A4
32
A5
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 1:0
Address Bus 11:0
125
29
122
27
141
A6
A7
A8
A9
A10
AP
A11
A12
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Bus 11:0
118
115
Address Signal 12
Note: Module based on
256 Mbit or larger
dies
Note: 128 Mbit based
module
Address Signal 13
Note: 1 Gbit based
module
Note: Module based on
512 Mbit or smaller
dies
NC
NC
167
A13
I
SSTL
NC
NC
Data Signals
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Pin
#
Name
Pin
Type
Buffer
Type
Function
相關(guān)PDF資料
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