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參數(shù)資料
| 型號： | HYS72D64300HBR-7-C |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 184-Pin Registered Double Data Rate SDRAM Module |
| 中文描述： | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | GREEN, DIMM-184 |
| 文件頁數(shù)： | 12/50頁 |
| 文件大?。?/td> | 1158K |
| 代理商： | HYS72D64300HBR-7-C |
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Internet Data Sheet
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
12
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Input High (Logic1) Voltage
Input Low (Logic0) Voltage
Input Voltage Level, CK and
CK Inputs
Input Differential Voltage, CK
and CK Inputs
VI-Matching Pull-up Current
to Pull-down Current
Input Leakage Current
V
IH(DC)
V
IL(DC)
V
IN(DC)
V
REF
+ 0.15
–
0.3
–
0.3
—
—
—
V
DDQ
+ 0.3
V
REF
– 0.15
V
DDQ
+ 0.3
V
V
V
6)
6)
6)
V
ID(DC)
0.36
—
V
DDQ
+ 0.6
V
6)7)
VI
Ratio
0.71
—
1.4
—
8)
I
I
–2
—
2
μ
A
Any input 0 V
≤
V
IN
≤
V
DD
; All
other pins not under test = 0 V
6)9)
Output Leakage Current
I
OZ
–5
—
5
μ
A
DQs are disabled; 0 V
≤
V
OUT
≤
V
DDQ
V
OUT
= 1.95 V
Output High Current, Normal
Strength Driver
Output Low Current, Normal
Strength Driver
1) 0
°
C
≤
T
A
≤
70
°
C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions,
V
DDQ
must be less than or equal to
V
DD
.
4) Peak to peak AC noise on
V
REF
may not exceed ± 2%
V
REF (DC)
.
V
REF
is also expected to track noise variations in
V
DDQ
.
5)
V
is not applied directly to the device.
V
TT
is a system supply for signal termination resistors, is expected to be set equal to
V
REF
, and
must track variations in the DC level of
V
REF
.
6) Inputs are not recognized as valid until
V
REF
stabilizes.
7)
V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
8) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and
voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
9) Values are shown per DDR SDRAM component
I
OH
—
—
–16.2
mA
I
OL
16.2
—
—
mA
V
OUT
= 0.35 V
Parameter
Symbol
Values
Unit
Note
1)
/Test Condition
Min.
Typ.
Max.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72D64320 | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64320HBR-5-C | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64320HBR-6-C | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64300HU-5-C | 184-Pin Unbuffered Double Data Rate SDRAM |
| HYS72D64300HU-6-C | 184-Pin Unbuffered Double Data Rate SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72D64300HU-5-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:42184-Pin Unbuffered Double-Data-Rate Memory Modules |
| HYS72D64300HU-5-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Unbuffered Double Data Rate SDRAM |
| HYS72D64300HU-6-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules |
| HYS72D64300HU-6-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Unbuffered Double Data Rate SDRAM |
| HYS72D64301 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184 - Pin Registered Double-Data-Rate SDRAM Module |
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