- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370782 > HYB18T512160AF-3 (INFINEON TECHNOLOGIES AG) 512-Mbit DDR2 SDRAM PDF資料下載
參數(shù)資料
| 型號： | HYB18T512160AF-3 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512-Mbit DDR2 SDRAM |
| 中文描述： | 512兆位DDR2 SDRAM的 |
| 文件頁數(shù)： | 99/117頁 |
| 文件大?。?/td> | 2102K |
| 代理商： | HYB18T512160AF-3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁當前第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁
Data Sheet
99
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Electrical Characteristics
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
t
QH
t
QHS
t
REFI
t
HP
–
t
QHS
340
—
—
105
0.9
0.40
7.5
10
7.5
0.35
0.40
15
t
WR
/
t
CK
7.5
2
—
—
7.8
3.9
—
1.1
0.60
—
—
—
—
0.60
—
ps
μ
s
μ
s
ns
t
CK
t
CK
ns
ns
ns
t
CK
t
CK
ns
t
CK
ns
t
CK
13)14)
13)15)
Auto-Refresh to Active/Auto-Refresh command period
Read preamble
Read postamble
Active bank A to Active bank B command period
t
RFC
t
RPRE
t
RPST
t
RRD
1)
12)
12)
16)17)
17)18)
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-Precharge
Write recovery time for write with Auto-Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read command (slow
exit, lower power)
Exit precharge power-down to any valid command (other
than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
1)
V
DDQ
= 1.8 V ± 0.1 V;
V
DD
= 1.8 V ± 0.1 V. See notes
3)4)5)6)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8 of this data sheet. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1
= 0) under the Reference Load for Timing Measurements according to Chapter 8.1 only.
4) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.
The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode;
The input reference level for signals other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3 of this data
sheet.
5) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is
recognized as low.
6) The output timing reference voltage level is
V
TT
. See Chapter 8 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required as describes in Chapter 2.12.
9) For timing definition, Slew Rate and Slew Rate derating see Chapter 8.3
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS/DQS and associated DQ in any given cycle.
t
RTP
t
WPRE
t
WPST
t
WR
WR
t
WTR
t
XARD
19)
—
—
20)
21)
t
XARDS
7 – AL
—
t
CK
21)
t
XP
2
—
t
CK
t
XSNR
t
XSRD
t
RFC
+10
200
—
—
ns
t
CK
Table 53
Parameter
Timing Parameter by Speed Grade - DDR2-667
Symbol
DDR2-667
Min.
Unit
Note
1)2)3)4)5)6)
Max.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB18T512160AF-3.7 | 512-Mbit DDR2 SDRAM |
| HYB18T512160AF-3S | 512-Mbit DDR2 SDRAM |
| HYB18T512400AF-3 | 512-Mbit DDR2 SDRAM |
| HYB18T512400AF-3S | 512-Mbit DDR2 SDRAM |
| HYB18T512800AF-3 | 512-Mbit DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
| HYB18T512400AF-5 | 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA |
| HYB18T512400BF-3S | 制造商:Qimonda 功能描述: |
| HYB18T512800AF-3S | 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| HYB18T512800BF-2.5 | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。