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參數(shù)資料
| 型號(hào)： | HYB18T512160AF-3.7 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512-Mbit DDR2 SDRAM |
| 中文描述： | 512兆位DDR2 SDRAM的 |
| 文件頁(yè)數(shù)： | 62/117頁(yè) |
| 文件大小： | 2102K |
| 代理商： | HYB18T512160AF-3.7 |
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Data Sheet
62
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
3.23
Auto-Precharge Operation
Before a new row in an active bank can be opened, the
active bank must be precharged using either the Pre-
charge Command or the Auto-Precharge function.
When a Read or a Write Command is given to the
DDR2 SDRAM, the CAS timing accepts one extra
address, column address A10, to allow the active bank
to automatically begin precharge at the earliest
possible moment during the burst read or write cycle. If
A10 is LOW when the Read or Write Command is
issued, then normal Read or Write burst operation is
executed and the bank remains active at the
completion of the burst sequence. If A10 is HIGH when
the Read or Write Command is issued, then the Auto-
Precharge function is enabled. During Auto-Precharge,
a Read Command will execute as normal with the
exception that the active bank will begin to precharge
internally on the rising edge which is CAS Latency (CL)
clock cycles before the end of the read burst. Auto-
Precharge is also implemented for Write Commands.
The Precharge operation engaged by the Auto-
Precharge command will not begin until the last data of
the write burst sequence is properly stored in the
memory array. This feature allows the precharge
operation to be partially or completely hidden during
burst read cycles (dependent upon CAS Latency) thus
improving system performance for random data
access. The RAS lockout circuit internally delays the
Precharge operation until the array restore operation
has been completed so that the Auto-Precharge
command may be issued with any read or write
command.
3.23.1
Read with Auto-Precharge
If A10 is 1 when a Read Command is issued, the Read
with Auto-Precharge function is engaged. The DDR2
SDRAM starts an Auto-Precharge operation on the
rising edge which is (AL + BL/2) cycles later from the
Read with AP command if
t
RAS.MIN
and
t
RTP
are
satisfied. If
t
RAS.MIN
is not satisfied at the edge, the start
point of Auto-Precharge operation will be delayed until
t
RAS.MIN
is satisfied. If
t
RTP.MIN
is not satisfied at the edge,
the start point of Auto-Precharge operation will be
delayed until
t
RTP.MIN
is satisfied.
In case the internal precharge is pushed out by
t
RTP
,
t
RP
starts at the point where the internal precharge
happens (not at the next rising clock edge after this
event). So for BL = 4 the minimum time from Read with
Auto-Precharge to the next Activate command
becomes AL +
t
RTP
+
t
RP
. For BL = 8 the time from Read
with Auto-Precharge to the next Activate command is
AL + 2 +
t
RTP
+
t
RP
. Note that (
t
RTP
+
t
RP
) has to be
rounded up to the next integer value. In any event
internal precharge does not start earlier than two clocks
after the last 4-bit prefetch.
A new bank active command may be issued to the
same bank if the following two conditions are satisfied
simultaneously:
1. The RAS precharge time (
t
RP
) has been satisfied
from the clock at which the Auto-Precharge begins.
2. The RAS cycle time (
t
RC
) from the previous bank
activation has been satisfied.
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