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參數(shù)資料
| 型號： | HY62V16100LR2-I-12 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 120 ns, PDSO44 |
| 封裝： | 0.400 INCH, REVERSE, TSOP2-44 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 151K |
| 代理商： | HY62V16100LR2-I-12 |
HY62V16100-(I)/HY62U16100-(I) Series
Rev.07 /Jan.99
4
AC CHARACTERISTICS(I)
Vcc = 3.3V
±
10%, T
A
= 0
°
C to 70
°
C (Normal)/ -40
°
C to 85
°
C (E.T.), unless otherwise specified
-85
-10
-12
Min.
Max.
Min.
Max.
Min
Max.
1
2
3
4
5
6
7
8
9
10
11
12
tRC
tAA
tACS
tOE
tBA
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
tBHZ
tOH
WRITE CYCLE
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
/LB, /UB Access Time
Chip Select to Output in Low Z
Output Enable to Output in Low Z
/LB. /UB Enable to Output in Low Z
Chip Deselection to Output in High Z
Out Disable to Output in High Z
/LB, /UB Disable to Output in High Z
Output Hold from Address Change
85
-
-
-
-
10
10
10
0
0
0
20
-
100
-
-
-
-
10
10
10
0
0
0
20
-
120
-
-
-
-
10
10
10
0
0
0
20
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
85
85
45
45
-
-
-
30
30
30
-
100
100
50
50
-
-
-
30
30
30
-
120
120
60
60
-
-
-
40
40
40
-
13
14
15
16
17
18
19
20
21
22
23
tWC
tCW
tAW
tBW
tAS
tWP
tWR
tWHZ
tDW
tDH
tOW
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
/LB, /UB Valid to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
85
70
70
70
0
55
0
0
35
0
10
-
-
-
-
-
-
-
100
80
80
80
0
70
0
0
40
0
10
-
-
-
-
-
-
-
120
100
100
100
0
85
0
0
50
0
10
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
-
-
-
30
-
-
-
40
-
-
-
READ CYCLE
Symbol
Parameter
#
Unit
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