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參數(shù)資料
| 型號： | HY62QF16200ALLF-I-10 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 16 STANDARD SRAM, 100 ns, PBGA48 |
| 封裝： | FINE PITCH, BGA-48 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 143K |
| 代理商： | HY62QF16200ALLF-I-10 |
HY62QF16200A Series
Rev.04 /Jun. 2000
6
WRITE CYCLE 1
ADDR
CS
Data
Out
tWC
tDW
tOHZ(3,9)
WE
Data Valid
tDH
tWP(1)
tAS
Data In
tCW
tWR(2)
tBW
tAS
tAW
UB,LB
WRITE CYCLE 2 (Note 5)
tDW
tWHZ
WE
Data Valid
tDH
tWP
tAS
Data In
tWR
tCW
tAW
(6)
(7)
tWHZ
ADDR
CS
Data
Out
tWC
Notes:
1. A write occurs during the overlap(tWP) of a low /CS and low /WE
.
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the /WE
transition, outputs remain in a high impedance state.
5. /OE is continuously low(/OE=VIL)
6. Q(data out) is the same phase with the write data of this write cycle.
7. Q(data out) is the read data of the next address.
8. If /CS is low during this period, I/O pins are in the output state.
Then the data input signals of opposite phase to the outputs must not be applied to them.
9. Transition is measured +200mV from steady state.
This parameter is sampled and not 100% tested.
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